Fermi surface mapping from the one-dimensional fourier transform of compton profiles

The structures of various ordered, but non-periodic, systems have been investigated and exhibit features which can be directly described by means of a construction which the authors call the shift lattice , which is a simple generalization of the concept of the lattice. This paper is devoted to a description of the properties of the one-dimensional shift lattice and its Fourier transform. Its applications to the phases related to L–Ta 2 O 5 and some Bi 2 TeO 5 -related systems are outlined and its relation to the theory of modulated structures and their Fourier transforms is briefly discussed.

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A power-aware IP core generator for the one-dimensional discrete Fourier transform

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328827 ◽

2004 ◽

Author(s):

Chih-Da Chien ◽

Chien-Chang Lin ◽

Jiun-In Guo ◽

Tien-Fu Chen

Keyword(s):

Fourier Transform ◽

Discrete Fourier Transform ◽

Ip Core ◽

One Dimensional ◽

The One

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A new hardware efficient design for the one dimensional discrete Fourier transform

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1010762 ◽

2003 ◽

Author(s):

Jiun-In Guo ◽

Chien-Chang Lin

Keyword(s):

Fourier Transform ◽

Discrete Fourier Transform ◽

Efficient Design ◽

One Dimensional ◽

The One

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A LOW-POWER PARAMETERIZED HARDWARE DESIGN FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM OF VARIABLE LENGTHS

Journal of Circuits System and Computers ◽

10.1142/s0218126602000549 ◽

2002 ◽

Vol 11 (04) ◽

pp. 405-426 ◽

Cited By ~ 1

Author(s):

JIUN-IN GUO ◽

CHIEN-CHANG LIN ◽

CHIH-DA CHIEN

Keyword(s):

Fourier Transform ◽

Low Power ◽

Discrete Fourier Transform ◽

Hardware Design ◽

Ip Core ◽

Distributed Arithmetic ◽

One Dimensional ◽

System Requirements ◽

Block Based ◽

The One

This paper presents a new low-power parameterized hardware design for the one-dimensional (1D) discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic (BDA), and Cooley–Tukey decomposition algorithm together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance. The proposed design can perform different lengths of DFT computation through the configuration of parameters, which not only provides the flexibility in computing different length DFT but also facilitates the performance-driven design considerations in terms of power consumption and processing speeds, that is, we can configure the proposed design in different modes of performance by setting different parameters. This feature is beneficial to developing a parameterized DFT soft Intellectual Property (IP) core or hard IP core for meeting the system requirements of different silicon-on-a-chip (SOC) applications as compared with the existing fixed length DFT designs.

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