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Programmable System Level Integration Brings System-on-Chip Design to the Desktop
Lecture Notes in Computer Science - Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing
◽
10.1007/3-540-44614-1_86
◽
2000
◽
pp. 789-792
Author(s):
Guy Lecurieux Lafayette
Keyword(s):
System On Chip
◽
System Level
◽
Chip Design
◽
On Chip
Download Full-text
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References
Extend Force-directed Scheduling for System-level Synthesis in Timeconstrained System-on-Chip Design
Second International Conference on Embedded Software and Systems (ICESS'05)
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10.1109/icess.2005.54
◽
2006
◽
Author(s):
Renfa Li Qiang Wu
Keyword(s):
System On Chip
◽
System Level
◽
Chip Design
◽
On Chip
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A system-level simulation environment for system-on-chip design
Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)
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10.1109/asic.2000.880676
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2002
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Cited By ~ 2
Author(s):
T. Schneider
◽
J. Mades
◽
A. Windisch
◽
M. Glesner
◽
D. Monjau
◽
...
Keyword(s):
System On Chip
◽
System Level
◽
Simulation Environment
◽
Chip Design
◽
System Level Simulation
◽
On Chip
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System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
◽
10.1109/ahs.2007.102
◽
2007
◽
Cited By ~ 5
Author(s):
A. Ahmadinia
◽
B. Ahmad
◽
T. Arslan
Keyword(s):
System On Chip
◽
System Level
◽
Chip Design
◽
On Chip
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Developing silicon intellectual property E-trade mechanisms for system on chip design and integration
International Journal of Computer Integrated Manufacturing
◽
10.1080/09511920601160122
◽
2007
◽
Vol 20
(5)
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pp. 423-435
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Cited By ~ 1
Author(s):
C. V. Trappey
◽
A. J. C. Trappey
◽
F. T. L. Lin
Keyword(s):
Intellectual Property
◽
System On Chip
◽
Chip Design
◽
On Chip
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Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design
2012 25th International Conference on VLSI Design
◽
10.1109/vlsid.2012.31
◽
2012
◽
Cited By ~ 1
Author(s):
Susmita Sur-Kolay
◽
S. Bhunia
Keyword(s):
Intellectual Property
◽
System On Chip
◽
Intellectual Property Protection
◽
Chip Design
◽
On Chip
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System Architecting and System-on-Chip Design of Intelligent Sensor Networks for Active Volcanoes
2008 2nd Annual IEEE Systems Conference
◽
10.1109/systems.2008.4519025
◽
2008
◽
Cited By ~ 2
Author(s):
Wai-Chi Fang
◽
Sharon Kedar
Keyword(s):
Sensor Networks
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System On Chip
◽
Chip Design
◽
Intelligent Sensor
◽
On Chip
◽
Intelligent Sensor Networks
◽
Active Volcanoes
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A Modular and Distributed Setup for Power and Performance Analysis of Multi-Processor System-on-Chip at Electronic System Level
2020 IEEE 39th International Performance Computing and Communications Conference (IPCCC)
◽
10.1109/ipccc50635.2020.9391516
◽
2020
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Author(s):
Muhammad Mudussir Ayub
◽
Franz Kreupl
Keyword(s):
Performance Analysis
◽
Electronic System
◽
System On Chip
◽
System Level
◽
Electronic System Level
◽
And Performance
◽
On Chip
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High Level System-on-Chip Design using UML and SystemC
Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007)
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10.1109/cerma.2007.4367776
◽
2007
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Cited By ~ 1
Author(s):
Blanca Alicia Correa
◽
Juan Fernando Eusse
◽
Danny Munera
◽
Jose Edinson Aedo
◽
Juan Fernando Velez
Keyword(s):
System On Chip
◽
Level System
◽
Chip Design
◽
On Chip
◽
High Level
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IP development and management of IP DB enabling efficient system-on-chip design
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)
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10.1109/apasic.1999.824070
◽
2003
◽
Cited By ~ 1
Author(s):
Young-ho Lee
◽
Ki-Won Kwon
◽
Jin-Tea Kim
◽
Chul-Dong Lee
Keyword(s):
System On Chip
◽
Chip Design
◽
Efficient System
◽
On Chip
◽
Development And Management
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Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
EDA for IC Implementation, Circuit Design, and Process Technology
◽
10.1201/9781420007954-23
◽
2018
◽
pp. 23_1-23_25
Author(s):
Nishath Verghese
◽
Makoto Nagata
Keyword(s):
System On Chip
◽
Chip Design
◽
Mixed Signal
◽
Signal Noise
◽
Noise Coupling
◽
Modeling Analysis
◽
On Chip
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