Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

Location-Aware Node Management Solution for Multi-Radio Dual Connectivity Scenarios

The location of user equipments (UEs) allows application developers to customize the services for users to perceive an enhanced experience. In addition, this UE location enables network operators to develop location-aware solutions to optimize network resource management. Moreover, the combination of location-aware approaches and new network features introduced by 5G enables to further improve the network performance. In this sense, dual connectivity (DC) allows users to simultaneously communicate with two nodes. The basic strategy proposed by 3GPP to select these nodes is based only on the power received by the users. However, the network performance could be enhanced if an alternative methodology is proposed to make this decision. This paper proposes, instead of power-based selection, to choose the nodes that provide the highest quality of experience (QoE) to the user. With this purpose, the proposed system uses the UE location as well as multiple network metrics as inputs. A dense urban scenario is assumed to test the solution in a system-level simulation tool. The results show that the optimal selection varies depending on the UE location, as well as the increase in the QoE perceived by users of different services.

Multi-Connectivity Enhanced Communication-Incentive Distributed Computation Offloading in Vehicular Networks

Flexible resource scheduling and network forecast are crucial functions to enhance mobile vehicular network performances. However, BaseStations (BSs) and their computing unit which undertake the functions cannot meet the delay requirement because of limited computation capability. Offloading the time-sensitive functions to User Equipment (UE) is believed to be an effective method to tackle this challenge. The disadvantage of the method is offloading occupies communication resources, which deteriorate the system capability. To better coordinate offloading and communication, a multi-connectivity enhanced joint scheduling scheme for distributed computation offloading and communication resources allocation in vehicular networks is proposed in this article. Computation tasks are divided into many slices and distributed to UEs to aggregate the computation capability. A communication-incentive mechanism is provided for involving UEs to compensate the loss of UEs, while multi-connectivity is adopted to enhance the system throughput. We also defined offloading failure ratio as a conclusive condition for offloading size by analyzing the movement of UEs. By a two-step optimization, the co-scheduling of offloading size and throughput is solved. The system-level simulation results show that the offloading size and throughput of the proposed scheme are larger than comparisons when the time constraint is tight.

Massive MIMO Adaptive Modulation and Coding Using Online Deep Learning

The paper describes an online deep learning algorithm for the adaptive modulation and coding in 5G Massive MIMO. The algorithm is based on a fully connected neural network, which is initially trained on the output of the traditional algorithm and then is incrementally retrained by the service feedback of its output. We show the advantage of our solution over the state-of-the-art Q-Learning approach. We provide system-level simulation results to support this conclusion in various scenarios with different channel characteristics and different user speeds. Compared with traditional OLLA our algorithm shows 10% to 20% improvement of user throughput in full buffer case. <br>

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Gem5-X

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this article, we present gem5-X, a system-level simulation framework, based on gem-5, for architectural exploration of heterogeneous many-core systems. To demonstrate the capabilities of gem5-X, real-time video analytics is used as a case-study. It is composed of two kernels, namely, video encoding and image classification using convolutional neural networks (CNNs). First, we explore through gem5-X the benefits of latest 3D high bandwidth memory (HBM2) in different architectural configurations. Then, using a two-step exploration methodology, we develop a new optimized clustered-heterogeneous architecture with HBM2 in gem5-X for video analytics application. In this proposed clustered-heterogeneous architecture, ARMv8 in-order cluster with in-cache computing engine executes the video encoding kernel, giving 20% performance and 54% energy benefits compared to baseline ARM in-order and Out-of-Order systems, respectively. Furthermore, thanks to gem5-X, we conclude that ARM Out-of-Order clusters with HBM2 are the best choice to run visual recognition using CNNs, as they outperform DDR4-based system by up to 30% both in terms of performance and energy savings.