A Modular VLSI Implementation Architecture for Communication Subsystems

The authors analyze different approaches to the study of the political system of society (PSO) in various social sciences. The prospects of an interdisciplinary study of PSO based on the llocation of several subsystems with various functions are substantiated. The characteristic of various functional subsystems of the PSO is given, among them: institutional, regulatory, ideological, technological, communication subsystems

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A New Design for 9/7-Tap Wavelet Filter and Its VLSI Implementation

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00411 ◽

2009 ◽

Vol 31 (3) ◽

pp. 411-418

Author(s):

Xin TIAN ◽

Yi-Hua TAN ◽

Jin-Wen TIAN

Keyword(s):

Vlsi Implementation ◽

Wavelet Filter

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ARPA/CSTO Rapid VLSI Implementation

10.21236/ada269170 ◽

1993 ◽

Author(s):

Cesar A. Pina

Keyword(s):

Vlsi Implementation

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

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DESIGNING A SYSTOLIC ALGORITHM FOR GENERATING WELL-FORMED PARENTHESIS STRINGS

Parallel Processing Letters ◽

10.1142/s0129626404001738 ◽

2004 ◽

Vol 14 (01) ◽

pp. 83-97

Author(s):

JONG-CHUANG TSAY

Keyword(s):

Linear Array ◽

Vlsi Implementation ◽

Processor Array ◽

Lexicographical Order ◽

Systolic Algorithm ◽

Left And Right ◽

Local Connection

A parenthesis string is a string of left and right parentheses. The string is well-formed when it consists of balanced pairs of left and right parentheses. This study presents a novel systolic algorithm for generating all the well-formed parenthesis strings in lexicographical order. The algorithm is cost-optimal and is run on a linear array of processors such that each well-formed parenthesis string can be generated in three time steps. The processor array is appropriate for VLSI implementation, since it has the features of modularity, regularity, and local connection.

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