Power-Efficient Cache Coherence

2004 ◽  
pp. 63-78 ◽  
Author(s):  
Craig Saldanha ◽  
Mikko H. Lipasti
Keyword(s):  
Cache Coherence ◽  
Power Efficient

Determination of Adjacent Nodes for Power Efficient Wireless Sensor Networks

2014 ◽  
Vol 134 (5) ◽  
pp. 612-619 ◽  
Author(s):  
Kohei Kamimura ◽  
Hitoshi Hayashi ◽  
Takaaki Hatauchi
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Wireless Sensor ◽  
Power Efficient

A POWER EFFICIENT NMOS BASED FULL ADDER USING PTL LOGIC

2017 ◽  
Vol 5 (4) ◽  
pp. 15
Author(s):  
ISWARIYA S. ◽  
RAJA M. VILASINI ◽  
◽  
Keyword(s):  
Full Adder ◽  
Power Efficient

THE PROBLEM OF PROVIDING CACHE COHERENCE IN MULTIPROCESSOR SYSTEMS WITH MANY PROCESSORS

2018 ◽  
pp. 47-53
Author(s):  
B. Z. Shmeylin ◽  
E. A. Alekseeva
Keyword(s):  
Cache Coherence ◽  
Bloom Filters ◽  
Multiprocessor Systems ◽  
Cache Line ◽  
Maintenance Systems ◽  
Processor Caches ◽  
Conventional Systems ◽  
Additional Hardware

In this paper the tasks of managing the directory in coherence maintenance systems in multiprocessor systems with a large number of processors are solved. In microprocessor systems with a large number of processors (MSLP) the problem of maintaining the coherence of processor caches is significantly complicated. This is due to increased traffic on the memory buses and increased complexity of interprocessor communications. This problem is solved in various ways. In this paper, we propose the use of Bloom filters used to accelerate the determination of an element’s belonging to a certain array. In this article, such filters are used to establish the fact that the processor belongs to some subset of the processors and determine if the processor has a cache line in the set. In the paper, the processes of writing and reading information in the data shared between processors are discussed in detail, as well as the process of data replacement from private caches. The article also shows how the addresses of cache lines and processor numbers are removed from the Bloom filters. The system proposed in this paper allows significantly speeding up the implementation of operations to maintain cache coherence in the MSLP as compared to conventional systems. In terms of performance and additional hardware and software costs, the proposed system is not inferior to the most efficient of similar systems, but on some applications and significantly exceeds them.

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