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A Single-Phase Energy Metering SoC with IAS-DSP and Ultra Low Power Metering Mode
Ultra-Low Power Integrated Circuit Design - Analog Circuits and Signal Processing
◽
10.1007/978-1-4419-9973-3_8
◽
2013
◽
pp. 169-195
Author(s):
Yan Zhao
◽
Shupeng Zhong
◽
Kun Yang
◽
Changyou Men
◽
Nianxiong Nick Tan
◽
...
Keyword(s):
Low Power
◽
Single Phase
◽
Ultra Low Power
◽
Energy Metering
◽
Power Metering
Download Full-text
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A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode
2011 IEEE International SOC Conference
◽
10.1109/socc.2011.6085091
◽
2011
◽
Cited By ~ 2
Author(s):
Yan Zhao
◽
Nianxiong Tan
◽
Kun Yang
◽
Shupeng Zhong
◽
Changyou Men
Keyword(s):
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◽
Single Phase
◽
Ultra Low Power
◽
Energy Metering
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Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop
10.1109/icecs53924.2021.9665485
◽
2021
◽
Author(s):
Yugal Maheshwari
◽
Kleber Stangherlin
◽
Derek Wright
◽
Manoj Sachdev
Keyword(s):
Low Power
◽
Single Phase
◽
Low Energy
◽
Flip Flop
◽
Ultra Low Power
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Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
IEEE Journal of Solid-State Circuits
◽
10.1109/jssc.2018.2875089
◽
2019
◽
Vol 54
(2)
◽
pp. 550-559
◽
Cited By ~ 11
Author(s):
Yunpeng Cai
◽
Anand Savanth
◽
Pranay Prabhat
◽
James Myers
◽
Alex S. Weddell
◽
...
Keyword(s):
Low Power
◽
Single Phase
◽
Flip Flop
◽
Ultra Low Power
Download Full-text
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
IEEE Transactions on Circuits and Systems I Regular Papers
◽
10.1109/tcsi.2009.2016183
◽
2010
◽
Vol 57
(1)
◽
pp. 72-82
◽
Cited By ~ 41
Author(s):
M.V. Krishna
◽
Manh Anh Do
◽
Kiat Seng Yeo
◽
Chirn Chye Boon
◽
Wei Meng Lim
Keyword(s):
Low Power
◽
Single Phase
◽
Ultra Low Power
◽
Phase Clock
Download Full-text
Improved Design of Ultra Low Power True Single Phase Clock CMOS 2/3 prescaler with 6 GHz, 199 µW
IJIREEICE
◽
10.17148/ijireeice.2017.5332
◽
2017
◽
Vol 5
(3)
◽
pp. 135-141
Author(s):
Roshan Kumar
◽
Prof. Monika Kapoor
Keyword(s):
Low Power
◽
Single Phase
◽
Ultra Low Power
◽
Phase Clock
◽
Improved Design
Download Full-text
Implementation of Ultra Low-Power 8 Bit CLA Using Single Phase Adiabatic Dynamic Logic
2010 International Conference on Advances in Recent Technologies in Communication and Computing
◽
10.1109/artcom.2010.82
◽
2010
◽
Author(s):
M. Chanda
◽
S. Naha
◽
S. Manna
◽
A. Dandapat
◽
H. Rahaman
Keyword(s):
Low Power
◽
Single Phase
◽
Dynamic Logic
◽
Ultra Low Power
Download Full-text
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas.2018.8350985
◽
2018
◽
Author(s):
Ming-Yan Tsai
◽
Po-Yu Kuo
◽
Jin-Fa Lin
◽
Ming-Hwa Sheu
Keyword(s):
Low Power
◽
Time Variation
◽
Single Phase
◽
Hold Time
◽
Reduction Scheme
◽
Flip Flop
◽
Ultra Low Power
◽
Logic Structure
Download Full-text
Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW
IJARCCE
◽
10.17148/ijarcce.2017.63106
◽
2017
◽
Vol 6
(3)
◽
pp. 459-464
Author(s):
Roshan Kumar
◽
Prof. Monika Kapoor
Keyword(s):
Low Power
◽
Single Phase
◽
Ultra Low Power
◽
Phase Clock
Download Full-text
Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL)
TENCON 2009 - 2009 IEEE Region 10 Conference
◽
10.1109/tencon.2009.5395803
◽
2009
◽
Cited By ~ 11
Author(s):
M. Chanda
◽
A. Dandapat
◽
H. Rahaman
Keyword(s):
Low Power
◽
Single Phase
◽
Dynamic Logic
◽
Circuit Implementation
◽
Sequential Circuit
◽
Ultra Low Power
Download Full-text
Ultra Low Power Bioelectronics
10.1017/cbo9780511841446
◽
2009
◽
Cited By ~ 187
Author(s):
Rahul Sarpeshkar
Keyword(s):
Low Power
◽
Ultra Low Power
Download Full-text
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