Model-Based Run-Time Synthesis of Architectural Configurations for Adaptive MILS Systems

2019 ◽  
pp. 200-215 ◽  
Author(s):  
Alessandro Cimatti ◽  
Rance DeLong ◽  
Ivan Stojic ◽  
Stefano Tonetta
Keyword(s):  
Model Based ◽  
Run Time

scholarly journals Model-Based Tool-Assistance for Packet-Filter Design and its Future

2014 ◽  
Vol 13 (1) ◽  
pp. 4053-4057
Author(s):  
Gurvinder Kaur ◽  
Dr. S.N. Panda ◽  
Dr. Dalvinder Singh Dhaliwal
Keyword(s):  
Filter Design ◽  
Packet Filtering ◽  
Packet Filter ◽  
Design Time ◽  
Model Based ◽  
Log Files ◽  
Run Time ◽  
Private Network ◽  
Is Design ◽  
Access Model

Firewall is a device that secure the private network from unauthorized access. Model based  tool assistance  facilitate the design task and has contribute to the correctness of the filters. But the model based tool assistance approach is design time only does not manage actions at run time. So we shall propose model on run time auditing architecture to detect the attack while packet filtering in firewall technology. It is usually based on the log-files of the packet-filters.

A Broader View on Context Models towards Supporting Business Process Agility

2011 ◽  
pp. 337-358 ◽  
Author(s):  
Barbara Thönssen ◽  
Daniela Wolff
Keyword(s):  
Business Process ◽  
Enterprise Architecture ◽  
Business Processes ◽  
Ad Hoc ◽  
Workflow Engine ◽  
Context Aware ◽  
Context Model ◽  
Model Based ◽  
Run Time ◽  
Context Models

Today’s enterprises need to be agile, to be able to cope with unexpected changes, to increasingly be dynamic, and to continually deal with change. Change affecting business processes may range from ad hoc modification to process evolution. In this chapter we present dimensions of change concentrating on a specific ability of an enterprise to deal with change. To support business in being agile we propose a semantically enriched context model based on well known enterprise architecture. We present a context aware workflow engine basing on the context model and on rules which trigger process adaptations during run time.

scholarly journals BlackBox Model Based VLSI Hierarchical Floorplanning

2019 ◽  
Vol 8 (6) ◽  
pp. 2604-2607
Keyword(s):  
Physical Design ◽  
Design Flow ◽  
Prototype Model ◽  
Asic Design ◽  
Model Based ◽  
Initial Stage ◽  
Floor Planning ◽  
Run Time ◽  
Prototype Design

Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of Backbox model based top level hierarchical floorplanning based physical design. The main aim of this project is to reduce the number of instances which are not necessary in the top level chip floor planning which reduces peak memory for the design and also reducing CPU run time for getting proper prototype design in the top level ASIC design and estimate the congestion in the design at initial stage and modify floor planning to obtain quality of prototype model in the floorplanning. This project is designed on cadence encounter tool.

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