High-Level Simulation for Multiple Fault Injection Evaluation

Author(s):  
Maxime Puys ◽  
Lionel Rivière ◽  
Julien Bringer ◽  
Thanh-ha Le
Author(s):  
Jaan Raik ◽  
Urmas Repinski ◽  
Maksim Jenihhin ◽  
Anton Chepurov

This Chapter addresses the above-mentioned challenges by presenting a holistic diagnosis approach for design error location and malicious fault list generation for soft errors. First, a method for locating design errors at the source-level of hardware description language code using the design representation of high-level decision diagrams is explained. Subsequently, this method is reduced to malicious fault list generation at the high-level. A minimized fault list is generated for optimizing the time to be spent on the fault injection run necessary for assessing designs vulnerability to soft-errors.


Author(s):  
Jorge Tonfat ◽  
Jimmy Tarrillo ◽  
Lucas Tambara ◽  
Fernanda Lima Kastensmidt ◽  
Ricardo Reis

Author(s):  
DIMITER R. AVRESKY ◽  
PRADEEP K. TAPADIYA

This paper presents a multi-stage software design approach for fault-tolerance. In the first stage, a formalism is introduced to represent the behavior of the system by means of a set of assertions. This formalism enables an execution tree (ET) to be generated where each path from the root to the leaf is, in fact, a well-defined formula. During the automatic generation of the execution tree, properties like completeness and consistency of the set of assertions can be verified and consequently design faults can be revealed. In the second stage, the testing strategy is based on a set of WDFs. This set represents the structural deterministic test for the model of the software system and provides a framework for the generation of a functional deterministic test for the code implementation of the model. This testing strategy can reveal the implementation faults in the program code. In the third stage, the fault-tolerance of the software system against hardware failures is improved in a way such that the design and implementation features obtained from the first two stages are preserved. The proposed approach provides a high level of user-transparency by employing object-oriented principles of data encapsulation and polymorphism. The reliability of the software system against hardware failures is also evaluated. A tool, named Software Fault-Injection Tool (SFIT), is developed to estimate the reliability of a software system.


Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3028
Author(s):  
Hwisoo So ◽  
Moslem Didehban ◽  
Yohan Ko ◽  
Reiley Jeyapaul ◽  
Jongho Kim ◽  
...  

Aggressive technology scaling and near-threshold computing have made soft error reliability one of the leading design considerations in modern embedded microprocessors. Although traditional hardware/software redundancy-based schemes can provide a high level of protection, they incur significant overheads in terms of performance and hardware resources. The considerable overheads from such full redundancy-based techniques has motivated researchers to propose low-cost soft error protection schemes, such as symptom-based error protection schemes. The main idea behind a symptom-based error protection scheme is that soft errors in the system will quickly generate some symptoms, such as exceptions, branch mispredictions, cache or TLB misses, or unpredictable variable values. Therefore, monitoring such infrequent symptoms makes it possible to cover the manifestation of failures caused by soft errors. Symptom-based protection schemes have been suggested as shortcuts to achieve acceptable reliability with comparable overheads. Since the symptom-based protection schemes seem attractive due to their generality and simplicity, even state-of-the-art protection schemes exploit them as the baseline protections. However, our detailed analysis of the fault coverage and performance overheads of such schemes reveals that the user-visible failure coverage, particularly of ReStore, is limited (29% on average). By contrast, the runtime overheads are significant (40% on average) because the majority of the fault injection experiments, which were considered as detected/recovered failures by low-level symptoms, are actually benign faults by program-level masking effects.


Cryptography ◽  
2021 ◽  
Vol 5 (2) ◽  
pp. 15
Author(s):  
Jacob Grycel ◽  
Patrick Schaumont

Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of SimpliFI, describe automation of the simulation framework, and apply SimpliFI on a BRISC-V embedded processor running an AES application.


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