A Flexible High-Resolution Real-Time Low-Power Stereo Vision Engine

2015 ◽  
pp. 69-79 ◽  
Author(s):  
Stefan K. Gehrig ◽  
Reto Stalder ◽  
Nicolai Schneider
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Real Time ◽  
Stereo Vision

Real-time, High-resolution Depth Upsampling on Embedded Accelerators

2021 ◽  
Vol 20 (3) ◽  
pp. 1-22
Author(s):  
David Langerman ◽  
Alan George
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Real Time ◽  
Mixed Reality ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Reconfigurable Logic ◽  
Depth Sensors ◽  
Time Requirements ◽  
Graphics Processing

High-resolution, low-latency apps in computer vision are ubiquitous in today’s world of mixed-reality devices. These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps. 1

scholarly journals High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard

2010 ◽  
Vol 13 (3) ◽  
Author(s):  
Felipe Sampaio ◽  
Daniel Palomino ◽  
Robson Dornelles ◽  
Luciano Agostini
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Video Coding ◽  
Real Time ◽  
Video Compression ◽  
High Throughput ◽  
Low Cost ◽  
Standard Cell ◽  
Dedicated Hardware ◽  
Operation Frequency

This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this design is to achieve high throughput rates combined with low hardware consumption. The architecture was described in VHDL and synthesized to the EP2S60F1020C3 Altera Stratix II FPGA and to the TSMC 0.18μm Standard Cell technology. The architecture is able to operate at 364.2 MHz as a maximum operation frequency. At this frequency, the architecture is able to process 117 QHDTV frames (3840x2048 pixels) per second. The designed architecture can be used in low power and low cost applications, since it can process high resolution in real time even with very low operation frequencies and with low hardware consumption. In the comparison with related works, the designed Q module achieves the best results of throughput and hardware consumption.

Real-Time Low-Power FPGA Architecture for Stereo Vision

2017 ◽  
Vol 64 (11) ◽  
pp. 1307-1311 ◽  
Author(s):  
Luca Puglia ◽  
Mario Vigliar ◽  
Giancarlo Raiconi
Keyword(s):  
Low Power ◽  
Real Time ◽  
Stereo Vision ◽  
Fpga Architecture
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