Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 ◽  
Vol 43 (7) ◽  
pp. 151-160 ◽  
Author(s):  
Bjorn De Sutter ◽  
Paul Coene ◽  
Tom Vander Aa ◽  
Bingfeng Mei
2011 ◽  
Vol 57 (8) ◽  
pp. 761-777 ◽  
Author(s):  
Ricardo S. Ferreira ◽  
João M.P. Cardoso ◽  
Alex Damiany ◽  
Julio Vendramini ◽  
Tiago Teixeira

Author(s):  
Dennis Wolf ◽  
Andreas Engel ◽  
Tajas Ruschke ◽  
Andreas Koch ◽  
Christian Hochberger

AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.


2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Stefan Döbrich ◽  
Christian Hochberger

Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.


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