Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs

2003 ◽  
pp. 553-564 ◽  
Author(s):  
A. Benkrid ◽  
K. Benkrid ◽  
D. Crookes
Keyword(s):  
Fir Filter ◽  
Design And Implementation ◽  
Filter Architecture

scholarly journals FPGA implementation of folded FIR filter architecture with changeable folding factor

2002 ◽  
Vol 15 (3) ◽  
pp. 451-464 ◽  
Author(s):  
Ivan Milentijevic ◽  
Vladimir Ciric ◽  
Teufik Tokic ◽  
Oliver Vojinovic
Keyword(s):  
Original Data ◽  
Fir Filter ◽  
Data Flow Graph ◽  
Fixed Size ◽  
Flow Graph ◽  
Filter Architecture ◽  
Fir Filtering ◽  
Bit Plane ◽  
Design Tradeoffs ◽  
Folding Factor

The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor on to the fixed size array is described in this paper. The bit-level transformation of the original data flow graph (DFG), for the bit-plane architecture, that provides the successful application of the folding technique with changeable folding is presented at transfer function level The mathematical path that describes the transformation is given, and implications at the DFG level are discussed. Changeable folding sets are involved with aim to increase the throughput of the folded system reducing the folding factor according to the coefficient length. The folded FIR filter architecture is described in VHDL as a parameterized FIR filtering core and implemented in FPGA technology. The design "tradeoffs" relating on the occupation of the chip resources and achieved throughputs are presented.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

Design and implementation of ALU-based FIR filter

2021 ◽  
pp. 702-707
Author(s):  
Ruqaiya Khanam ◽  
Gitanjali Mehta ◽  
Rani Astya
Keyword(s):  
Fir Filter ◽  
Design And Implementation
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