Design and Implementation of FIR Filter Architecture Using High Level Transformation Techniques

Abstract Although ecological momentary assessment (EMA) has been used in youth and adult populations, very few of the studies provided evidence of the feasibility and utility of smartphone-based EMA protocols to collect biopsychosocial data from aging populations. This study aimed to describe the design and implementation of a smartphone-based EMA protocol, and to evaluate the feasibility and utility of this EMA protocol among community-dwelling late-middle-aged and older Chinese. A sample of 78 community-dwelling Chinese aged between 50 and 70 years was trained to participate in a 1-week EMA data collection, during which each participant carried an Android smartphone loaded with a researcher-developed EMA application and a smartphone-based electrocardiogram (ECG) monitor to provide psychosocial (e.g., daily activities, social interaction, affect) data and ECG recordings six times daily. Adherence was demonstrated with a total response rate of 91.5% of all scheduled assessments (n = 3,822) and a moderately high level of perceived feasibility. Female participants reported higher compliance to the study and rated the overall experience as more pleasant and interesting than male participants. Our study provided the first evidence of the feasibility and utility of smartphone-based EMA protocols among late-middle-aged and older Chinese. Key areas for improvement in future design and implementation of mobile-based EMA include the incorporation of usable technology, adequate and training, and timely assistance.

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FPGA implementation of folded FIR filter architecture with changeable folding factor

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee0203451m ◽

2002 ◽

Vol 15 (3) ◽

pp. 451-464 ◽

Cited By ~ 1

Author(s):

Ivan Milentijevic ◽

Vladimir Ciric ◽

Teufik Tokic ◽

Oliver Vojinovic

Keyword(s):

Original Data ◽

Fir Filter ◽

Data Flow Graph ◽

Fixed Size ◽

Flow Graph ◽

Filter Architecture ◽

Fir Filtering ◽

Bit Plane ◽

Design Tradeoffs ◽

Folding Factor

The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor on to the fixed size array is described in this paper. The bit-level transformation of the original data flow graph (DFG), for the bit-plane architecture, that provides the successful application of the folding technique with changeable folding is presented at transfer function level The mathematical path that describes the transformation is given, and implications at the DFG level are discussed. Changeable folding sets are involved with aim to increase the throughput of the folded system reducing the folding factor according to the coefficient length. The folded FIR filter architecture is described in VHDL as a parameterized FIR filtering core and implemented in FPGA technology. The design "tradeoffs" relating on the occupation of the chip resources and achieved throughputs are presented.

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The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.571.534 ◽

2012 ◽

Vol 571 ◽

pp. 534-537

Author(s):

Bao Feng Zhang ◽

De Hu Man ◽

Jun Chao Zhu

Keyword(s):

Signal Processing ◽

Real Time ◽

Field Programmable Gate Array ◽

Distributed Algorithm ◽

Design Method ◽

Fir Filter ◽

Experimental Results ◽

Linear Phase ◽

Design And Implementation ◽

Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

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