scholarly journals Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses

2008 ◽  
pp. 121-134 ◽  
Author(s):  
Ariel Cohen ◽  
Amir Pnueli ◽  
Lenore D. Zuck
Keyword(s):  
Transactional Memory ◽  
Mechanical Verification ◽  
Memory Accesses ◽  
Transactional Memories

Hardware Transactional Memories

2016 ◽  
pp. 47-65
Author(s):  
Arsalan Shahid ◽  
Maryam Murad ◽  
Muhammad Yasir Qadri ◽  
Nadia N. Qadri ◽  
Jameel Ahmed
Keyword(s):  
Shared Memory ◽  
Transactional Memory ◽  
Mutual Exclusion ◽  
Multithreaded Programming ◽  
Shared Data ◽  
Suboptimal Solution ◽  
Thread Level Parallelism ◽  
Level Parallelism ◽  
Work Done ◽  
Transactional Memories

The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.

scholarly journals Accelerating GPU Hardware Transactional Memory with Snapshot Isolation

2017 ◽  
Vol 45 (2) ◽  
pp. 282-294 ◽  
Author(s):  
Sui Chen ◽  
Lu Peng ◽  
Samuel Irving
Keyword(s):  
Transactional Memory ◽  
Hardware Transactional Memory ◽  
Snapshot Isolation

Adaptive Precision Block-Jacobi for High Performance Preconditioning in the Ginkgo Linear Algebra Software

2021 ◽  
Vol 47 (2) ◽  
pp. 1-28
Author(s):  
Goran Flegar ◽  
Hartwig Anzt ◽  
Terry Cojean ◽  
Enrique S. Quintana-Ortí
Keyword(s):  
Linear Algebra ◽  
Graphics Processing Units ◽  
High Performance ◽  
Numerical Algorithms ◽  
Mixed Precision ◽  
Before And After ◽  
Memory Accesses ◽  
Specialized Hardware ◽  
The Individual ◽  
Graphics Processing

The use of mixed precision in numerical algorithms is a promising strategy for accelerating scientific applications. In particular, the adoption of specialized hardware and data formats for low-precision arithmetic in high-end GPUs (graphics processing units) has motivated numerous efforts aiming at carefully reducing the working precision in order to speed up the computations. For algorithms whose performance is bound by the memory bandwidth, the idea of compressing its data before (and after) memory accesses has received considerable attention. One idea is to store an approximate operator–like a preconditioner–in lower than working precision hopefully without impacting the algorithm output. We realize the first high-performance implementation of an adaptive precision block-Jacobi preconditioner which selects the precision format used to store the preconditioner data on-the-fly, taking into account the numerical properties of the individual preconditioner blocks. We implement the adaptive block-Jacobi preconditioner as production-ready functionality in the Ginkgo linear algebra library, considering not only the precision formats that are part of the IEEE standard, but also customized formats which optimize the length of the exponent and significand to the characteristics of the preconditioner blocks. Experiments run on a state-of-the-art GPU accelerator show that our implementation offers attractive runtime savings.

scholarly journals Linear capabilities for fully abstract compilation of separation-logic-verified code

2021 ◽  
Vol 31 ◽  
Author(s):  
THOMAS VAN STRYDONCK ◽  
FRANK PIESSENS ◽  
DOMINIQUE DEVRIESE
Keyword(s):  
Spatial Separation ◽  
Separation Logic ◽  
Target Language ◽  
Fine Grained ◽  
Dynamic Contract ◽  
Modular Verification ◽  
Source Program ◽  
Memory Accesses ◽  
Memory Resources ◽  
Efficient Memory

Abstract Separation logic is a powerful program logic for the static modular verification of imperative programs. However, dynamic checking of separation logic contracts on the boundaries between verified and untrusted modules is hard because it requires one to enforce (among other things) that outcalls from a verified to an untrusted module do not access memory resources currently owned by the verified module. This paper proposes an approach to dynamic contract checking by relying on support for capabilities, a well-studied form of unforgeable memory pointers that enables fine-grained, efficient memory access control. More specifically, we rely on a form of capabilities called linear capabilities for which the hardware enforces that they cannot be copied. We formalize our approach as a fully abstract compiler from a statically verified source language to an unverified target language with support for linear capabilities. The key insight behind our compiler is that memory resources described by spatial separation logic predicates can be represented at run time by linear capabilities. The compiler is separation-logic-proof-directed: it uses the separation logic proof of the source program to determine how memory accesses in the source program should be compiled to linear capability accesses in the target program. The full abstraction property of the compiler essentially guarantees that compiled verified modules can interact with untrusted target language modules as if they were compiled from verified code as well. This article is an extended version of one that was presented at ICFP 2019 (Van Strydonck et al., 2019).

scholarly journals Revisiting software transactional memory in Haskell

2018 ◽  
Vol 51 (12) ◽  
pp. 105-113
Author(s):  
Matthew Le ◽  
Ryan Yates ◽  
Matthew Fluet
Keyword(s):  
Transactional Memory ◽  
Software Transactional Memory

Starvation-free commit arbitration policies for transactional memory systems

2007 ◽  
Vol 35 (1) ◽  
pp. 39-46 ◽  
Author(s):  
M. M. Waliullah ◽  
Per Stenstrom
Keyword(s):  
Transactional Memory ◽  
Memory Systems

Analysing software prefetching opportunities in hardware transactional memory

2021 ◽  
Author(s):  
Marina Shimchenko ◽  
Rubén Titos-Gil ◽  
Ricardo Fernández-Pascual ◽  
Manuel E. Acacio ◽  
Stefanos Kaxiras ◽  
...  
Keyword(s):  
Transactional Memory ◽  
Hardware Transactional Memory ◽  
Software Prefetching

scholarly journals Supporting nested transactional memory in logTM

2006 ◽  
Vol 40 (5) ◽  
pp. 359-370 ◽  
Author(s):  
Michelle J. Moravan ◽  
Jayaram Bobba ◽  
Kevin E. Moore ◽  
Luke Yen ◽  
Mark D. Hill ◽  
...  
Keyword(s):  
Transactional Memory
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