Internet of Things Applications

The Internet of Things (IoT) brings connectivity to about every objects found in the physical space. It extends connectivity not only to computer and mobile devices but also to everyday objects. From connected fridges, cars and cities, the IoT creates opportunities in numerous domains. This chapter briefly surveys some IoT applications and the impact the IoT could have on societies. It shows how the various application of the IoT enhances the overall quality of life and reduces management and costs in various sectors.

High Performance Computing on Mobile Devices

Mobile devices are gaining high popularity due to support for a wide range of applications. However, the mobile devices are resource constrained and many applications require high resources. To cater to this issue, the researchers envision usage of mobile cloud computing technology which offers high performance computing, execution of resource intensive applications, and energy efficiency. This chapter highlights importance of mobile devices, high performance applications, and the computing challenges of mobile devices. It also provides a brief introduction to mobile cloud computing technology, its architecture, types of mobile applications, computation offloading process, effective offloading challenges, and high performance computing application on mobile devises that are enabled by mobile cloud computing technology.

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

CPU-GPU Computing

Heterogeneous and hybrid computing has been heavily studied in the field of parallel and distributed computing in recent years. It can work on a single computer, or in a group of computers connected by a high-speed network. The former is the topic of this chapter. Its key points are how to cooperatively use devices that are different in performance and architecture to satisfy various computing requirements, and how to make the whole program achieve the best performance possible when executed. CPUs and GPUs have fundamentally different design philosophies, but combining their characteristics could avail better performance in many applications. However, it is still a challenge to optimize them. This chapter focuses on the main optimization strategies including “partitioning and load-balancing”, “data access”, “communication”, and “synchronization and asynchronization”. Furthermore, two applications will be introduced as examples of using these strategies.

Multicore and Manycore

This chapter presents an overview of the evolution of computer architecture, giving special attention on those advances which have promoted the current hybrid systems. After that, we focus on the most extended programming strategies applied to hybrid computing. In fact, programming is one of the most important challenges for this kind of systems, as it requires a high knowledge of the hardware to achieve a good performance. Current hybrid systems are basically composed by three components, two processors (multicore and manycore) and an interconnection bus (PCIe), which connects both processors. Each of the components must be managed differently. After presenting the particular features of current hybrid systems, authors focus on introducing some approaches to exploit simultaneously each of the components. Finally, to clarify how to program in these platforms, two cases studies are presented and analyzed in deep. At the end of the chapter, authors outline the main insights behind hybrid computing and introduce upcoming advances in hybrid systems.

A Theoretic Representation of the Effects of Targeted Failures in HPC Systems

High performance computing (HPC) systems are becoming the norm for daily use and care must be made to ensure that these systems are resilient. Recent contributions on resiliency have been from quantitative and qualitative perspectives where general system failures are considered. However, there are limited contributions dealing with the specific classes of failures that are directly related to cyber-attacks. In this chapter, the author uses the concepts of transition processes and limiting distributions to perform a generic theoretical investigation of the effects of targeted failures by relating the actions of the cyber-enemy (CE) to different risk levels in an HPC system. Special cases of constant attack strategies are considered where exact solutions are obtained. Additionally, a stopped process is introduced to model the effects of system termination. The results of this representation can be directly applied throughout the HPC community for monitoring and mitigating cyber-attacks.

Design Space Exploration Using Cycle Accurate Simulator

Multi-Processor System on Chip (MPSoC) architectures have become a mainstream technology for obtaining performance improvements in computing platforms. With the increase in the number of cores, the role of cache memory has become pivotal. An ideal memory configuration is always desired to be fast and large; but, in fact, striking to balance between the size and access time of the memory hierarchy is considered by processor architect. Design space exploration is used for performance analysis of systems and helps to find the optimal solution for obtaining the desired objectives. In this chapter, we explore two design space parameters, i.e., cache size and number of cores, for obtaining the desired energy consumption. Moreover, previously presented energy models for multilevel cache are evaluated by using cycle accurate full system simulator. Our results show that with the increase in cache sizes, the number of cycles required for application execution decreases, and by increasing number of cores, the throughput improve.

Verification of Super-Peer Model for Query Processing in Peer-to-Peer Networks

Equal peers in peer-to-peer (P2P) networks are the drawbacks of system in term of bandwidth, scalability and efficiency. The super-peer model is based on heterogeneity and different characteristics of peers in P2P networks. The P2P networks and large- scale distributed systems based on P2P networks use the super-peer model to design the query processing mechanism. This chapter first reviews the query processing methods in P2P networks, in which the authors classify theses query processing approaches in Unstructured and Structured mechanisms. Furthermore, the query processing techniques in distributed systems based on P2P networks are discussed. Afterward, authors concentrate on super-peer model to process the query of peers in P2P networks. Authors present the query processing methods in P2P-based distributed systems using the super node. Finally, the chapter provides some examples of each of the presented query processing techniques, and then illustrates the properties of each of them in terms of scalability and performance issues.

Fault Tolerance Techniques for Distributed, Parallel Applications

This chapter gives an overview of techniques used to tolerate failures in high-performance distributed applications. We describe basic replication techniques, automatic rollback recovery and application-based fault tolerance. We present the challenges raised specifically by distributed, high performance computing and the performance overhead the fault tolerance mechanisms are likely to cost. Last, we give an example of a fault-tolerant algorithm that exploits specific properties of a recent algorithm.

Task-Based Crowd Simulation for Heterogeneous Architectures

Industry trends in the coming years imply the availability of cluster computing with hundreds to thousands of cores per chip, as well as the use of accelerators. Programming presents a challenge due to this heterogeneous architecture; thus, using novel programming models that facilitate this process is necessary. In this chapter, the case of simulation and visualization of crowds is presented. The authors analyze and compare the use of two programming models: OmpSs and CUDA. OmpSs allows to take advantage of all the resources available per node by combining the CPU and GPU while automatically taking care of memory management, scheduling, communications and synchronization. Experimental results obtained from Fermi, Kepler and Maxwell GPU architectures are presented, and the different modes used for visualizing the results are described, as well.