scholarly journals Workcraft: A Static Data Flow Structure Editing, Visualisation and Analysis Tool

2007 ◽  
pp. 505-514 ◽  
Author(s):  
Ivan Poliakov ◽  
Danil Sokolov ◽  
Andrey Mokhov
Keyword(s):  
Flow Structure ◽  
Data Flow ◽  
Analysis Tool ◽  
Static Data

A computational model for static data flow machines

1995 ◽  
Vol 21 (6) ◽  
pp. 483-497
Author(s):  
Fathy E. Eassa ◽  
M.M. Eassa ◽  
M. Zaki
Keyword(s):  
Computational Model ◽  
Data Flow ◽  
Static Data

Test sequence selection based on static data flow analysis

1987 ◽  
Vol 10 (5) ◽  
pp. 234-242 ◽  
Author(s):  
Hasan Ural
Keyword(s):  
Data Flow ◽  
Flow Analysis ◽  
Test Sequence ◽  
Data Flow Analysis ◽  
Static Data ◽  
Sequence Selection

scholarly journals Applications of Synchronized Pushdown Systems

2020 ◽  
pp. 19-45
Author(s):  
Johannes Späth
Keyword(s):  
Data Flow ◽  
Flow Analysis ◽  
Computational Effort ◽  
Pointer Analysis ◽  
Sensitive Data ◽  
Data Flow Analysis ◽  
Context Sensitive ◽  
Program Slice ◽  
Static Data ◽  
Per Se

AbstractA precise static data-flow analysis transforms the program into a context-sensitive and field-sensitive approximation of the program. It is challenging to design an analysis of this precision efficiently due to the fact that the analysis is undecidable per se. Synchronized pushdown systems (SPDS) present a highly precise approximation of context-sensitive and field-sensitive data-flow analysis. This chapter presents some data-flow analyses that SPDS can be used for. Further on, this chapter summarizes two other contributions of the thesis “Synchronized Pushdown System for Pointer and Data-Flow Analysis” called Boomerang and IDEal. Boomerang is a demand-driven pointer analysis that builds on top of SPDS and minimizes the highly computational effort of a whole-program pointer analysis by restricting the computation to the minimal program slice necessary for an individual query. IDEal is a generic and efficient framework for data-flow analyses, e.g., typestate analysis. IDEal resolves pointer relations automatically and efficiently by the help of Boomerang. This reduces the burden of implementing pointer relations into an analysis. Further on, IDEal performs strong updates, which makes the analysis sound and precise.

Cyclo-static data flow

2002 ◽  
Author(s):  
G. Bilsen ◽  
M. Engels ◽  
R. Lauwereins ◽  
J.A. Peperstraete
Keyword(s):  
Data Flow ◽  
Static Data

DroidRista: a highly precise static data flow analysis framework for android applications

2019 ◽  
Vol 19 (5) ◽  
pp. 523-536
Author(s):  
Areej Alzaidi ◽  
Suhair Alshehri ◽  
Seyed M. Buhari
Keyword(s):  
Data Flow ◽  
Flow Analysis ◽  
Analysis Framework ◽  
Data Flow Analysis ◽  
Static Data ◽  
Android Applications

Tokenless static data flow using associative templates

2003 ◽  
Author(s):  
T.L. Sterling ◽  
D.S. Wills ◽  
E.Y. Chan
Keyword(s):  
Data Flow ◽  
Static Data

Geometric parallelism and cyclo-static data flow in GRAPE-II

2002 ◽  
Author(s):  
R. Lauwereins ◽  
P. Wauters ◽  
M. Ade ◽  
J.A. Peperstraete
Keyword(s):  
Data Flow ◽  
Static Data

scholarly journals An Improved Data Flow Architecture for Logic Simulation Acceleration

VLSI Design ◽  
1994 ◽  
Vol 2 (3) ◽  
pp. 259-265
Author(s):  
A. Mahmood ◽  
J. Herath ◽  
J. Jayasumana
Keyword(s):  
Data Flow ◽  
Distribution Networks ◽  
Communication Overhead ◽  
Simulation Algorithm ◽  
Logic Simulation ◽  
Fast Evaluation ◽  
Digital Vlsi ◽  
Static Data ◽  
Event Driven ◽  
High Degree

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architecture to reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principle use a static data flow architecture along with a timing wheel mechanism to implement the event driven simulation algorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulation throughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitration and distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, three major improvements are made to the design of a classical data flow based logic simulation accelerator. These include:1) A novel and efficient technique for implementing a pseudo-dynamic data flow architecture to increase pipelining.2) Implementation of a modified distributed event driven simulation algorithm.3) Localized processors for fast evaluation of small primitives.

scholarly journals PERANCANGAN DAN PEMBUATAN CASE TOOL SOFTWARE TESTING MENGGUNAKAN METODE STATIC DATA FLOW ANALYSIS (STUDI KASUS POGRAM BERBASIS C++)

2005 ◽  
Vol 4 (1) ◽  
pp. 60
Author(s):  
Yudhi Purwananto ◽  
Arif Bramantoro ◽  
Luluk Harini
Keyword(s):  
Software Testing ◽  
Data Flow ◽  
Flow Analysis ◽  
Case Tool ◽  
Data Flow Analysis ◽  
Static Data
Sign in / Sign up

Export Citation Format

Share Document