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PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
◽
10.1007/978-3-540-95948-9_22
◽
2009
◽
pp. 219-228
Author(s):
Alberto García-Ortiz
◽
Leandro S. Indrusiak
◽
Tudor Murgan
◽
Manfred Glesner
Keyword(s):
Low Power
◽
Networks On Chip
◽
Virtual Channels
◽
On Chip
◽
Power Code
Download Full-text
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References
Low-Power Coding for Networks-on-Chip with Virtual Channels
Journal of Low Power Electronics
◽
10.1166/jolpe.2009.1006
◽
2009
◽
Vol 5
(1)
◽
pp. 77-84
◽
Cited By ~ 10
Author(s):
Alberto García-Ortiz
◽
Leandro S. Indrusiak
◽
Tudor Murgan
◽
Manfred Glesner
Keyword(s):
Low Power
◽
Networks On Chip
◽
Virtual Channels
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The case for low-power photonic networks on chip
2007 44th ACM/IEEE Design Automation Conference
◽
10.1145/1278480.1278513
◽
2007
◽
Cited By ~ 39
Author(s):
Assaf Shacham
◽
Keren Bergman
◽
Luca P. Carloni
Keyword(s):
Low Power
◽
Photonic Networks
◽
Networks On Chip
◽
On Chip
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Simulation environment for link energy estimation in networks-on-chip with virtual channels
Integration
◽
10.1016/j.vlsi.2019.05.005
◽
2019
◽
Vol 68
◽
pp. 147-156
◽
Cited By ~ 1
Author(s):
Jan Moritz Joseph
◽
Lennart Bamberg
◽
Imad Hajjar
◽
Robert Schmidt
◽
Thilo Pionteck
◽
...
Keyword(s):
Simulation Environment
◽
Energy Estimation
◽
Networks On Chip
◽
Virtual Channels
◽
On Chip
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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands
Integration
◽
10.1016/j.vlsi.2011.11.010
◽
2012
◽
Vol 45
(3)
◽
pp. 271-281
◽
Cited By ~ 7
Author(s):
Nishit Kapadia
◽
Sudeep Pasricha
Keyword(s):
Low Power
◽
Interconnection Networks
◽
Networks On Chip
◽
On Chip
◽
Low Power Synthesis
◽
Voltage Islands
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Supervised sharing of virtual channels in Networks -on-Chip
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014)
◽
10.1109/sies.2014.6871197
◽
2014
◽
Cited By ~ 5
Author(s):
Adam Kostrzewa
◽
Sebastian Tobuschat
◽
Phillip Axer
◽
Rolf Ernst
Keyword(s):
Networks On Chip
◽
Virtual Channels
◽
On Chip
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Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/2733374
◽
2015
◽
Vol 20
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◽
pp. 1-33
◽
Cited By ~ 4
Author(s):
Fahimeh Jafari
◽
Zhonghai Lu
◽
Axel Jantsch
Keyword(s):
Delay Bound
◽
Networks On Chip
◽
Virtual Channels
◽
Flows In Networks
◽
On Chip
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A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
2009 IEEE Computer Society Annual Symposium on VLSI
◽
10.1109/isvlsi.2009.19
◽
2009
◽
Cited By ~ 81
Author(s):
Huaxi Gu
◽
Kwai Hung Mo
◽
Jiang Xu
◽
Wei Zhang
Keyword(s):
Low Power
◽
Optical Networks
◽
Low Cost
◽
Multiprocessor Systems
◽
Optical Router
◽
Networks On Chip
◽
Systems On Chip
◽
On Chip
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Virtual channels in networks on chip
2005 18th Symposium on Integrated Circuits and Systems Design
◽
10.1145/1081081.1081128
◽
2005
◽
Cited By ~ 52
Author(s):
Aline Mello
◽
Leonel Tedesco
◽
Ney Calazans
◽
Fernando Moraes
Keyword(s):
Networks On Chip
◽
Virtual Channels
◽
On Chip
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High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels
Proceedings of 2010 IEEE International Symposium on Circuits and Systems
◽
10.1109/iscas.2010.5537747
◽
2010
◽
Cited By ~ 1
Author(s):
Yiping Dong
◽
Zhen Lin
◽
Yan Li
◽
Takahiro Watanabe
Keyword(s):
Neural Networks
◽
High Performance
◽
Networks On Chip
◽
Virtual Channels
◽
On Chip
Download Full-text
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science
◽
10.1007/978-3-642-17752-1_16
◽
2011
◽
pp. 160-169
Author(s):
Alberto Garcia-Ortiz
◽
Leandro S. Indrusiak
Keyword(s):
Low Power
◽
Networks On Chip
◽
On Chip
◽
Theoretical Considerations
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