On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks

2009 ◽  
pp. 145-156 ◽  
Author(s):  
Ricardo Ferreira ◽  
Alex Damiany ◽  
Julio Vendramini ◽  
Tiago Teixeira ◽  
João M. P. Cardoso
Keyword(s):  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 ◽  
Vol 43 (7) ◽  
pp. 151-160 ◽  
Author(s):  
Bjorn De Sutter ◽  
Paul Coene ◽  
Tom Vander Aa ◽  
Bingfeng Mei
Keyword(s):  
Register Allocation ◽  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing

scholarly journals Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks

2011 ◽  
Vol 57 (8) ◽  
pp. 761-777 ◽  
Author(s):  
Ricardo S. Ferreira ◽  
João M.P. Cardoso ◽  
Alex Damiany ◽  
Julio Vendramini ◽  
Tiago Teixeira
Keyword(s):  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing ◽  
Fast Placement

scholarly journals UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

2021 ◽  
Author(s):  
Dennis Wolf ◽  
Andreas Engel ◽  
Tajas Ruschke ◽  
Andreas Koch ◽  
Christian Hochberger
Keyword(s):  
Computing System ◽  
Coarse Grained ◽  
Instruction Level Parallelism ◽  
Control Engineering ◽  
Processing Elements ◽  
Actual Application ◽  
Reconfigurable Arrays ◽  
Engineering Environment ◽  
On Chip ◽  
Level Parallelism

AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays

2021 ◽  
Author(s):  
Xinyuan Wang ◽  
Tianyi Yu ◽  
Hsuan Hsiao ◽  
Jason Anderson
Keyword(s):  
Coarse Grained ◽  
Area Reduction ◽  
Reconfigurable Arrays

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays

2017 ◽  
Vol 28 (1) ◽  
pp. 29-43 ◽  
Author(s):  
Chen Yang ◽  
Leibo Liu ◽  
Kai Luo ◽  
Shouyi Yin ◽  
Shaojun Wei
Keyword(s):  
Coarse Grained ◽  
Improve Performance ◽  
Cache Partitioning ◽  
Reconfigurable Arrays

Compiler assisted architectural exploration for coarse grained reconfigurable arrays

2007 ◽  
Author(s):  
Gregory Dimitroulakos ◽  
Nikos Kostaras ◽  
Michalis D. Galanis ◽  
Costas E. Goutis
Keyword(s):  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Architectural Exploration

scholarly journals Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays

2012 ◽  
Author(s):  
Hee-Seok Kim ◽  
Minwook Ahn ◽  
John A. Stratton ◽  
Wen-mei W. Hwu
Keyword(s):  
Coarse Grained ◽  
Design Evaluation ◽  
Reconfigurable Arrays ◽  
Compiler Framework

scholarly journals Low-Complexity Online Synthesis for AMIDAR Processors

2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Stefan Döbrich ◽  
Christian Hochberger
Keyword(s):  
Expert Knowledge ◽  
Low Complexity ◽  
Coarse Grained ◽  
Strong Impact ◽  
Reconfigurable Logic ◽  
Gate Arrays ◽  
Reconfigurable Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Synthesis Approach

Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.

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