Design Space Exploration of Power Efficient Cache Design Techniques

2011 ◽  
pp. 362-371
Author(s):  
Ashish Kapania ◽  
H. V. Ravish Aradhya
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Power Efficient ◽  
Cache Design ◽  
Design Techniques

scholarly journals Power Efficient Rapid Design Space Exploration of Integrated Scheduling and Module Selection in High Level Synthesis

2021 ◽  
Author(s):  
Pallabi Sarkar
Keyword(s):  
Power Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Optimal Solutions ◽  
Power Efficient ◽  
Pi Method ◽  
High Level

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

A Two-Level Cache Design Space Exploration System for Embedded Applications

2009 ◽  
Vol E92-A (12) ◽  
pp. 3238-3247
Author(s):  
Nobuaki TOJO ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Embedded Applications ◽  
Cache Design

scholarly journals Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications

2015 ◽  
Vol 14 (3) ◽  
pp. 1-25 ◽  
Author(s):  
Parinaz Sayyah ◽  
Mihai T. Lazarescu ◽  
Sara Bocchio ◽  
Emad Ebeid ◽  
Gianluca Palermo ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Power Efficient ◽  
Virtual Platform ◽  
Embedded Applications ◽  
Platform Based Design

scholarly journals Power Efficient Rapid Design Space Exploration of Integrated Scheduling and Module Selection in High Level Synthesis

2021 ◽  
Author(s):  
Pallabi Sarkar
Keyword(s):  
Power Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Optimal Solutions ◽  
Power Efficient ◽  
Pi Method ◽  
High Level

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

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