2015 19th International Symposium on VLSI Design and Test
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9781479917433
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Out of order floating point coprocessor for RISC V ISA

2015 ◽  
Author(s):  
Vinayak Patil ◽  
Aneesh Raveendran ◽  
P M Sobha ◽  
A David Selvakumar ◽  
D Vivian
Keyword(s):  
Floating Point

Thermal aware AND-OR-XOR network synthesis

2015 ◽  
Author(s):  
Priyanka Choudhury ◽  
Debanjali Nath ◽  
Vivek Rai ◽  
Sambhu Nath Pradhan
Keyword(s):  
Network Synthesis

Low power and hardware cost STUMPS BIST

2015 ◽  
Author(s):  
N Ravi Kiran ◽  
G Harish ◽  
A Karthik ◽  
Siva Yellampalli
Keyword(s):  
Low Power ◽  
Hardware Cost

Methodology for optimizing ESD protection for high speed LVDS based I/Os

2015 ◽  
Author(s):  
Vishnuram Abhinav ◽  
Amitabh Chatterjee ◽  
Dheeraj Kumar Sinha ◽  
Rajan Singh
Keyword(s):  
High Speed ◽  
Esd Protection
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