Descriptive Dynamic Logic and Its Application to Reflective Architectures

2002 ◽  
pp. 197-220
Author(s):  
Carles Sierra ◽  
Lluís Godo ◽  
Ramon Lopez De Mántaras ◽  
Maria Manzano
Keyword(s):  
Dynamic Logic

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals The Dynamic Logic of Policies and Contingent Planning

2019 ◽  
pp. 659-674
Author(s):  
Thomas Bolander ◽  
Thorsten Engesser ◽  
Andreas Herzig ◽  
Robert Mattmüller ◽  
Bernhard Nebel
Keyword(s):  
Dynamic Logic ◽  
Contingent Planning

Single event upsets in gallium arsenide dynamic logic

1994 ◽  
Vol 41 (6) ◽  
pp. 2244-2251 ◽  
Author(s):  
D.J. Fouts ◽  
T. Weatherford ◽  
D. McMorrow ◽  
J.S. Melinger ◽  
A.B. Campbell
Keyword(s):  
Gallium Arsenide ◽  
Dynamic Logic ◽  
Single Event ◽  
Single Event Upsets

Design of Buffer Circuit for Global Interconnects Using Adiabatic Dynamic Logic

2021 ◽  
Author(s):  
Himani Bhardwaj ◽  
Shruti Jain ◽  
Harsh Sohal
Keyword(s):  
Dynamic Logic ◽  
Global Interconnects
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