benchmark circuit
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Author(s):  
Suruchi Sharma ◽  
Santosh Kumar ◽  
Alok Kumar Mishra ◽  
D. Vaithiyanathan ◽  
Baljit Kaur
Keyword(s):  

2020 ◽  
Vol 12 (10) ◽  
pp. 1289-1295
Author(s):  
Suruchi Sharma ◽  
Santosh Kumar ◽  
Alok Kumar Mishra ◽  
D. Vaithiyanathan ◽  
Baljit Kaur

High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.


Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.


Author(s):  
Walter L. Neto ◽  
Vinicius N. Possani ◽  
Felipe S. Marranghello ◽  
Jody M. Matos ◽  
Andre I. Reis ◽  
...  

2017 ◽  
Vol 105 (6) ◽  
pp. 1087-1104 ◽  
Author(s):  
Sorin P. Voinigescu ◽  
Stefan Shopov ◽  
James Bateman ◽  
Hassan Farooq ◽  
James Hoffman ◽  
...  

2016 ◽  
Vol 19 (2) ◽  
pp. 5-15
Author(s):  
Anh Pham Lan Vu ◽  
Viet Quoc Le ◽  
Tu Phan Vu

This paper presents an application of the Radial Basis Function – Based Finite Difference Method (RBF-FD) to solving the electrical transient problems defined by the time-dependent ordinary differential equations. In this method, the finite difference approximations of first- and second-order derivatives in time domain are formalated the same as those in space domain based on the MQ (Multiquadrics) function presented in [1]. The MQ RBF-FD method are for the sake of evaluating the accuracy, effectiveness and applicability used to compute the transient voltages on the benchmark circuit and 220 kV three-phase transmission line of Viet Nam. Our numerical results are compared with those obtained by the analytical method, the traditional FD method and ATP/EMTP software. The compared results have been shown that the MQ RBF-FD method has accuracy that is higher than ones of the traditional numerical methods, especially with the optimal shape parameter.


Author(s):  
Amanpreet Kaur ◽  
Bishwajeet Pandey ◽  
Sunny Singh ◽  
Aditi Modgil ◽  
Kanika Garg

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