An Active Mixer Design For Down Conversion in 180 nm CMOS Technology for RFIC Applications

Author(s):  
B. H. Shraddha ◽  
Nalini C. Iyer
Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 954 ◽  
Author(s):  
Giovanni Piccinni ◽  
Claudio Talarico ◽  
Gianfranco Avitabile ◽  
Giuseppe Coviello

This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply.


2009 ◽  
Vol 19 (4) ◽  
pp. 227-229 ◽  
Author(s):  
Dukju Ahn ◽  
Dong-Wook Kim ◽  
Songcheol Hong

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