scholarly journals Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 954 ◽  
Author(s):  
Giovanni Piccinni ◽  
Claudio Talarico ◽  
Gianfranco Avitabile ◽  
Giuseppe Coviello
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Noise Figure ◽  
Cmos Technology ◽  
Third Order ◽  
Innovative Strategy ◽  
The Core ◽  
Mixer Design ◽  
Down Conversion ◽  
A Current

This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply.

scholarly journals Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology

2009 ◽  
Vol 2009 ◽  
pp. 1-7
Author(s):  
Chin-Lung Yang ◽  
Chih-Hsiang Peng ◽  
Yi-Chyun Chiang
Keyword(s):  
Phase Noise ◽  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Design Constraint ◽  
Single Sideband ◽  
Start Up ◽  
Low Phase Noise ◽  
Down Conversion

This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS cross-coupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental results show a conversion gain of 6.5 dB at 2.1 GHz associated with a single-sideband (SSB) noise figure of below 13 dB. The oscillator mixer also exhibits a tuning range of 184 MHz and a phase noise of −116 dBc/Hz at 1-MHz offset from the LO frequency of 6.8 GHz, and it consumes 11 mA from 1.8 V bias voltage.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

A High-Linear CMOS Down Conversion Mixer Using Adjusting the Second and Third-Order Harmonic in Transconductance Stage

2014 ◽  
Vol 24 (01) ◽  
pp. 1550002 ◽  
Author(s):  
Mina Amiri ◽  
Adib Abrishamifar
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Third Order ◽  
Cmos Mixer ◽  
Simulation Results ◽  
Down Conversion ◽  
Pmos Transistor

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

scholarly journals Wideband ring mixer for band #1 of MB-OFDM systems in 180 nm CMOS technology

2021 ◽  
Vol 72 (5) ◽  
pp. 323-329
Author(s):  
Abhay Chaturvedi ◽  
Mithilesh Kumar ◽  
Ram Swaroop Meena ◽  
Gaurav Kumar Sharma
Keyword(s):  
Integrated Circuit ◽  
Orthogonal Frequency Division Multiplexing ◽  
Noise Figure ◽  
Impedance Matching ◽  
Cmos Technology ◽  
Ofdm Systems ◽  
Ofdm System ◽  
Integrated Circuit Design ◽  
Wireless Receiver ◽  
Down Conversion

Abstract A wideband down conversion ring mixer is proposed for multi band orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm CMOS technology. The mixer is essentially used in a heterodyne wireless receiver to enhance the selectivity of the system. Being a nonlinear system, the mixer dominates the overall performance of the system. The design of down conversion mixer is the most challenging part of a receive chain. Wideband impedance matching always remains a challenge in any radio frequency integrated circuit design. This paper presents the design of a ring mixer with high linearity, wideband impedance matching using differential resistive impedance matching and without using any DC bias. The proposed mixer is tuned for a frequency of 3.432 GHz of band 1 of the MB-OFDM system. Mixer core is based on the FET ring mixer topology. The mixer is implemented in 180 nm CMOS technology. The mixer achieves the minimum conversion loss of 10.49 dB, 1 dB compression point (P1) of 12.40 dBm, third order input intercept point (IIP3) of 12.01 dBm, a minimum SSB noise figure of 8.99 dB, and S 11 of less than -10 dB over the frequency range of 0 to 13.61 GHz . The layout of the mixer records an active area of 183.75 μm 2 .

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  
Keyword(s):  
Noise Figure ◽  
Nonlinear Coefficient ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Third Order ◽  
Input Matching ◽  
Third Stage ◽  
Protection Circuits ◽  
Noise Amplifier

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

2018 ◽  
Vol 32 (06) ◽  
pp. 1850068 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Yueyue Li ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Maximal Gain ◽  
Resistance Structure

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
Vol 1 (2) ◽  
pp. 1-7
Author(s):  
Krishna B.T. ◽  
mohaseena Salma Shaik.
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high-frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals 0.5-7.5 GHZ LOW-POWER, INDUCTORLESS CURRENT FOLDED MIXER IN 0.18-μM CMOS FOR BROADBAND APPLICATIONS

2013 ◽  
pp. 112-116
Author(s):  
ZAHRA GHANE FASHTALI ◽  
MAHROKH MAGHSOODI ◽  
REZA EBRAHIMI ATANI ◽  
MEHRGAN MAHDAVI
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Process ◽  
Conversion Gain ◽  
Fully Differential ◽  
Dc Power ◽  
Maximum Conversion ◽  
Cell Topology ◽  
Down Conversion

A fully differential low-power down-conversion mixer using a TSMC 0.18-μm CMOS process is presented in this paper. The proposed mixer is based on a folded double-balanced Gilbert cell topology that enhances conversion gain and reduces power dissipation. Though, this mixer is designed for 5.8 GHz ISM band applications, but at 0.5-7.5 GHz, the proposed mixer exhibits a maximum conversion gain of 12dB, maximum IIP3 of -2.5 dBm, maximum input 1-dB compression point of -13 dBm, the minimum DSB noise figure of 9.2 dB and a dc power consumption of 2.52 mW at 1.8 V power supply. Also, this circuit architecture increases port-to-port isolations to above 140 dB. Moreover this mixer is suitable for broadband applications.

scholarly journals Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults

2013 ◽  
Vol 8 (1) ◽  
pp. 32-42
Author(s):  
Paulo M. Moreira e Silva ◽  
Fernando Rangel de Sousa
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Fully Integrated ◽  
Uncertainty Sources ◽  
Measurement Results ◽  
Noise Amplifier ◽  
A Current ◽  
Measured Input

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.

A 2.4 GHz Low Voltage Low Power Folded Down-Conversion Quadrature Mixer Design

2013 ◽  
Vol 760-762 ◽  
pp. 526-530
Author(s):  
Ming Li ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Folded Structure ◽  
Single Side ◽  
Mixer Design ◽  
Low Supply Voltage ◽  
Single Side Band ◽  
Down Conversion

This paper introduces a 2.4 GHz down-conversion quadrature mixer which applied in the Wireless Sensor Network (WSN). The mixer uses a folded structure which is modified based on the conventional Gilbert mixer. It is designed in 0.18μm RF CMOS process with a low supply voltage of 1V. The post-simulation results show that the mixer achieves a conversion gain (CG) of 9.0dB, the input 1dB compression point (IP1dB) of-7.6dBm, the third-order input intercept point (IIP3) of 2.2dBm, and the single side-band (SSB) noise figure (NF) is 13.9dB. The mixer core consumes current about 1.2mA from a 1V power supply.

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