Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms

Author(s):  
V. P. Roychowdhury ◽  
T. Kailath
2009 ◽  
Vol 7 ◽  
pp. 95-100 ◽  
Author(s):  
C. C. Sun ◽  
J. Götze

Abstract. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.


2002 ◽  
Vol 58 (9-10) ◽  
pp. 9
Author(s):  
Efim Grigor'evich Zelkin ◽  
Victor Filippovich Kravchenko ◽  
Miklhail Alekseevich Basarab

1989 ◽  
Author(s):  
SEUNGSOO LEE ◽  
GEORGE DULIKRAVICH ◽  
DANIEL DORNEY

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