Convergence of Some Iterative Algorithms for System of Generalized Set-Valued Variational Inequalities

In this article, we consider and study a system of generalized set-valued variational inequalities involving relaxed cocoercive mappings in Hilbert spaces. Using the projection method and Banach contraction principle, we prove the existence of a solution for the considered problem. Further, we propose an iterative algorithm and discuss its convergence. Moreover, we establish equivalence between the system of variational inequalities and altering points problem. Some parallel iterative algorithms are proposed, and the strong convergence of the sequences generated by these iterative algorithms is discussed. Finally, a numerical example is constructed to illustrate the convergence analysis of the proposed parallel iterative algorithms.

Parallel Jacobi EVD Methods on Integrated Circuits

Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

A VLSI design concept for parallel iterative algorithms

Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.