This paper reviews proposals for extensions to VHDL to support high-level modeling
and places them within a taxonomy that describes the modeling requirements they
address. Many of the proposals focus on object-oriented extensions, whereas this paper
argues that extension of VHDL to support high-level modeling requires a broader
review. The paper presents a detailed discussion of issues to be considered in adding
high-level modeling extensions to VHDL, including concurrency and communication,
abstraction using entity interfaces, object-oriented data modeling, encapsulation, signal
assignment semantics, shared variables, multiple inheritance, genericity and synthesis.
Emphasis is placed on the importance of designing simple orthogonal semantic
mechanisms that interact in well defined ways, and that integrate cleanly with existing
language features.
Principles for Language Extensions to VHDL to Support High-Level Modeling