Proceedings of EURO-DAC. European Design Automation Conference
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Published By IEEE Comput. Soc. Press

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Verification of a production cell controller using symbolic timing diagrams

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527458 ◽

2002 ◽

Cited By ~ 1

Author(s):

R. Schlor ◽

F. Korf

Keyword(s):

Timing Diagrams ◽

Cell Controller ◽

Production Cell

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A native process algebra for VHDL

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527439 ◽

2002 ◽

Author(s):

P.T. Breuer ◽

N.M. Madrid

Keyword(s):

Process Algebra

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A uniform design methodology for application specific digital integrated circuits in automotive applications

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527462 ◽

2002 ◽

Author(s):

J. Papanuskas ◽

B. Mossner ◽

T. Lindenkreuz ◽

J. Hanisch

Keyword(s):

Integrated Circuits ◽

Design Methodology ◽

Uniform Design ◽

Automotive Applications ◽

Digital Integrated Circuits ◽

Application Specific

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An approach for classification of integrated circuits by a knowledge conserving library concept

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527387 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Wagenblasst ◽

W. Thronicke

Keyword(s):

Integrated Circuits

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Device selection for system partitioning

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527381 ◽

2002 ◽

Author(s):

U. Weinmann ◽

O. Bringmann ◽

W. Rosenstiel

Keyword(s):

Device Selection ◽

Selection For ◽

System Partitioning

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Timing optimization by bit-level arithmetic transformations

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527388 ◽

2002 ◽

Cited By ~ 3

Author(s):

L. Rijnders ◽

Z. Sahraoui ◽

P. Six ◽

H. De Man

Keyword(s):

Timing Optimization

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Partial scan selection for user-specified fault coverage

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527395 ◽

2002 ◽

Author(s):

C. Gloster ◽

F. Brglez

Keyword(s):

Fault Coverage ◽

Partial Scan ◽

Selection For ◽

Partial Scan Selection

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Procedure exlining: a new system-level specification transformation

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527452 ◽

2002 ◽

Cited By ~ 3

Author(s):

F. Vahid

Keyword(s):

System Level ◽

New System

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VHDL quality: synthesizability, complexity and efficiency evaluation

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527448 ◽

2002 ◽

Cited By ~ 4

Author(s):

M. Mastretti ◽

M.L. Busi ◽

R. Sarvello ◽

M. Sturlesi ◽

S. Tomasello

Keyword(s):

Efficiency Evaluation

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Towards verifying VHDL descriptions of processors

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527438 ◽

2002 ◽

Cited By ~ 1

Author(s):

L. Arditi ◽

H. Collavizza

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Proceedings of EURO-DAC. European Design Automation ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Verification of a production cell controller using symbolic timing diagrams

A native process algebra for VHDL

A uniform design methodology for application specific digital integrated circuits in automotive applications

An approach for classification of integrated circuits by a knowledge conserving library concept

Device selection for system partitioning

Timing optimization by bit-level arithmetic transformations

Partial scan selection for user-specified fault coverage

Procedure exlining: a new system-level specification transformation

VHDL quality: synthesizability, complexity and efficiency evaluation

Towards verifying VHDL descriptions of processors

Proceedings of EURO-DAC. European Design Automation Conference
Latest Publications