Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations

2012 ◽  
Vol 31 (6) ◽  
pp. 2075-2091 ◽  
Author(s):  
Mahzad Azarmehr ◽  
Majid Ahmadi
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Number System ◽  
Fir Filter ◽  
Two Dimensional ◽  
Logarithmic Number System ◽  
Logarithmic Number ◽  
Fir Filter Design

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

scholarly journals VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

2020 ◽  
Vol 9 (3) ◽  
pp. 4131-4139
Keyword(s):  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Fir Filters ◽  
Binary Digit ◽  
Booth Multiplier ◽  
Speed Optimization ◽  
Fir Filter Design ◽  
Convolution Equations

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

scholarly journals EFFICIENT FINITE IMPULSE RESPONSE FILTER ARCHITECTURE USING MULTIPLE CONSTANT MULTIPLICATION AND COMMON SUB-EXPRESSION ELIMINATION TECHNIQUES

2017 ◽  
Vol 10 (13) ◽  
pp. 344
Author(s):  
Bhargav Shukla ◽  
Augusta Sophy Beulet
Keyword(s):  
Impulse Response ◽  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Computationally Efficient ◽  
Constant Multiplication ◽  
Dsp Systems ◽  
Fir Filter Design

This paper introduces the computationally efficient, low power, high-speed partial reconfigurable finite impulse response (FIR) filter design usingmultiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by MCM operation. Forthe better performance of DSP systems, MCM operation is not sufficient. To get better results, some other operations are used with MCM. That’s why,this paper introduces a common sub-expression elimination operation of FIR filter design can be solved by decreasing the number of operators. Usingthese techniques shows the efficiency by reducing area when compared to previously used algorithms designed.

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