Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

scholarly journals FIR Filter Design using Finfets at 22nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1292-1295
Keyword(s):  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Fir Filters ◽  
Short Channel ◽  
Channel Effects ◽  
Complex Circuits ◽  
Fir Filter Design

Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing.In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used.Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter.As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.

scholarly journals Design of Finite Impulse Response Filters Based on Genetic Algorithm

2013 ◽  
Vol 6 (3) ◽  
pp. 28-39
Author(s):  
Raaed Faleh Hassan ◽  
Ali Subhi Abbood
Keyword(s):  
Genetic Algorithm ◽  
Impulse Response ◽  
Optimization Problems ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Optimal Solution ◽  
Fir Filter ◽  
Language Version ◽  
Finite Impulse Response Filters ◽  
Matlab Programming

Genetic Algorithms (GAs) are used to solve many optimization problems in science and engineering such as pattern recognition, robotics, biology, medicine, and many other applications. The aim of this paper is to describe a method of designing Finite Impulse Response (FIR) filter using Genetic Algorithm (GA). In this paper, the Genetic Algorithm not only used for searching the optimal coefficients, but also it is used to find the minimum number of Taps, and hence minimize the number of multipliers and adders that can be used in the design of the FIR filter. The Evolutionary Programming is the best search procedure and most powerful than Linear Programming in providing the optimal solution that is desired to minimize the ripple content in both passband and stopband. The algorithm generates a population of genomes that represents the filter coefficient and the number of taps, where new genomes are generated by crossover and mutation operations methods. Our proposed genetic technique has able to give better result compare to other method.The FIR filter design using Genetic Algorithm is simulated using MATLAB programming language version 7.6.0.324 (R2008a).

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

2020 ◽  
Vol 9 (3) ◽  
pp. 4131-4139
Keyword(s):  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Fir Filters ◽  
Binary Digit ◽  
Booth Multiplier ◽  
Speed Optimization ◽  
Fir Filter Design ◽  
Convolution Equations

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

scholarly journals Low power and area efficient design of fir filter using enhanced clock gating technique

2021 ◽  
Vol 9 ◽  
Author(s):  
L Mohana Kannan ◽  
◽  
Deepa D ◽  
Keyword(s):  
Transfer Functions ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Research Work ◽  
Fir Filter ◽  
Vlsi Circuits ◽  
Vlsi Circuit ◽  
Efficient Design ◽  
Clock Gating ◽  
Ripple Carry Adder

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

scholarly journals EFFICIENT FINITE IMPULSE RESPONSE FILTER ARCHITECTURE USING MULTIPLE CONSTANT MULTIPLICATION AND COMMON SUB-EXPRESSION ELIMINATION TECHNIQUES

2017 ◽  
Vol 10 (13) ◽  
pp. 344
Author(s):  
Bhargav Shukla ◽  
Augusta Sophy Beulet
Keyword(s):  
Impulse Response ◽  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Computationally Efficient ◽  
Constant Multiplication ◽  
Dsp Systems ◽  
Fir Filter Design

This paper introduces the computationally efficient, low power, high-speed partial reconfigurable finite impulse response (FIR) filter design usingmultiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by MCM operation. Forthe better performance of DSP systems, MCM operation is not sufficient. To get better results, some other operations are used with MCM. That’s why,this paper introduces a common sub-expression elimination operation of FIR filter design can be solved by decreasing the number of operators. Usingthese techniques shows the efficiency by reducing area when compared to previously used algorithms designed.

scholarly journals A Low Power FIR Filter Design for Image Processing

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 391-397 ◽  
Author(s):  
Jun Mo Jung ◽  
Jong-Wha Chong
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Filter Design ◽  
Design Method ◽  
Low Power Design ◽  
Fir Filter ◽  
Correlated Data ◽  
Clock Signal ◽  
Clock Gating ◽  
Flip Flop

In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to the correlation characteristic of its input space. For the sub-register which highly correlated data is inputted into, the dynamic power consumption is reduced by diminishing switching activity of the clock signal. We can also reduce the additional hardware overhead by propagating the clock gating control signal of the first tap register to other tap registers. To identify the efficiency of the proposed design method, we perform the experiments on some filters that are designed in VHDL. The power estimation tool says that the proposed method can reduce the power dissipation of the filter by more than 18% compared to the conventional filter design methods.

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