An Efficient Block-Based Architecture for Reconfigurable FIR Filter Using Partial-Product Method

The Rredundant Binary (RB) systems are wellliked for the reason that of its distinctive carry broadcast free addition. Thus a specific filter called as Finite Impulse Response filter computes its yield exploitation multiply& accumulation process. At intervals the reward work, a FIR filter supported to new higher radix-256 and chemical element arithmetic is implemented. The employment of radix-256 booth secret writing cut down the amount of partial product rows in any multiplication by eight fold. Present work inputs and coefficients unit of measurement thought-about of 16-bit. Hence, entirely two partial product rows unit of quantity obtained in Redundant Binary (RB) kind for both input and constant multiplications. These two partial product rows unit of measurement added exploitation carry free element addition. The final output is converted back to Natural Binary (NB). The planned number technique for FIR filter is compared with Computation Sharing Multiplier (CSHM) implementation.

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HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA

Journal of Circuits System and Computers ◽

10.1142/s0218126610006207 ◽

2010 ◽

Vol 19 (02) ◽

pp. 503-517

Author(s):

SHIANN-SHIUN JENG ◽

HSING-CHEN LIN ◽

CHUN-CHYUAN CHEN ◽

SHU-MING CHANG

Keyword(s):

Hardware Implementation ◽

Fir Filter ◽

Partial Product ◽

Distributed Arithmetic ◽

Clock Rate ◽

Parallel Multiplier

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case M = 2). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers.

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Transition analysis on FPGA for multiplier-block based FIR filter structures

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445) ◽

10.1109/icecs.2000.913012 ◽

2002 ◽

Cited By ~ 9

Author(s):

S.S. Demirsoy ◽

A. Dempster ◽

I. Kale

Keyword(s):

Fir Filter ◽

Transition Analysis ◽

Block Based ◽

Filter Structures

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Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

Microprocessors and Microsystems ◽

10.1016/j.micpro.2020.103113 ◽

2020 ◽

Vol 76 ◽

pp. 103113

Author(s):

T.V. Padmavathy ◽

S. Saravanan ◽

M.N. Vimalkumar

Keyword(s):

Fir Filter ◽

Ecg Signal ◽

Partial Product ◽

Ripple Carry Adder ◽

Filter Architecture

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Structured design of a 288-tap FIR filter by optimized partial product tree compression

IEEE Journal of Solid-State Circuits ◽

10.1109/4.557651 ◽

1997 ◽

Vol 32 (3) ◽

pp. 468-476 ◽

Cited By ~ 20

Author(s):

Jun Rim Choi ◽

Lak Hyun Jang ◽

Seong Wook Jung ◽

Jin Ho Choi

Keyword(s):

Fir Filter ◽

Partial Product ◽

Structured Design ◽

Tree Compression

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Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.12.16511 ◽

2018 ◽

Vol 7 (3.12) ◽

pp. 826

Author(s):

Suji S ◽

Radhika P

Keyword(s):

Hardware Implementation ◽

Fir Filter ◽

Power Reduction ◽

The Other ◽

Filter Length ◽

Filter Architecture ◽

Block Based ◽

Efficient Power

In this paper, a reconfigurable block FIR filter which supports variable filter length is proposed. This recon-figurable block FIR filter uses block based design. Hence, this is an algorithm free architecture. This proposed filter can be used for 5G air interface.The proposed filter produces more efficient power reduction than that of the other filter.The number of LUTs and registers are also reduced in the reconfigurable block FIR filter. The designed filter has been implemented in the ZYNQ xc7020 hardware device using the vivado 2015.4.The technique used for hardware implementation is the IP creation and debug-ging.The debugging helps in the monitoring and triggering the hardware device.

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