A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

2012 ◽  
Vol 41 (4) ◽  
pp. 491-534 ◽  
Author(s):  
N. Izeboudjen ◽  
C. Larbes ◽  
A. Farah
2020 ◽  
Vol 2020 ◽  
pp. 1-10
Author(s):  
Wei Wang ◽  
Yiyang Hu ◽  
Ting Zou ◽  
Hongmei Liu ◽  
Jin Wang ◽  
...  

Because deep neural networks (DNNs) are both memory-intensive and computation-intensive, they are difficult to apply to embedded systems with limited hardware resources. Therefore, DNN models need to be compressed and accelerated. By applying depthwise separable convolutions, MobileNet can decrease the number of parameters and computational complexity with less loss of classification precision. Based on MobileNet, 3 improved MobileNet models with local receptive field expansion in shallow layers, also called Dilated-MobileNet (Dilated Convolution MobileNet) models, are proposed, in which dilated convolutions are introduced into a specific convolutional layer of the MobileNet model. Without increasing the number of parameters, dilated convolutions are used to increase the receptive field of the convolution filters to obtain better classification accuracy. The experiments were performed on the Caltech-101, Caltech-256, and Tubingen animals with attribute datasets, respectively. The results show that Dilated-MobileNets can obtain up to 2% higher classification accuracy than MobileNet.


Author(s):  
Anne Marie Chana ◽  
Patrice Quinton ◽  
Steven Derrien

International audience The growing complexity of new chips and the time-to-market constraints require fundamental changes in the way systems are designed. Systems on Chip (SoC) based on reused components have become an absolute necessity to embedded systems companies that want to remain competitive. However, the design of a SoC is extremely complex because it encompasses a range of difficult problems in hardware and software design. This paper focuses on the design of parallel and multi-frequency applications using flexible components. Flexible parallel components are assembled using a scheduling method which combines the synchronous data-flow principle of balance equations and the polyhedral scheduling technique. Our approach allows a flexible component to be modelled and a full system to be assembled and synthesized with automatically generated wrappers. The work presented here is an extension of previous work. We illustrate our method on a simplified WCDMA system. We discuss the relationship of this approach with multi-clock architecture, latency-insensitive design, multidimensional data-flow systems and stream programming


2013 ◽  
pp. 275-285 ◽  
Author(s):  
Abderrazak Jemai ◽  
Kamel Smiri ◽  
Habib Smei

Task migration has a great consideration is MPSoC design and implementation of embedded systems in order to improve performance related to optimizing execution time or reducing energy consumption. Multi-Processor Systems-on-Chip (MPSoC) are now the leading hardware platform featured in embedded systems. This chapter deals with the impact of task migration as an alternative to meet performance constraints in the design flow. The authors explain the different levels of the design process and propose a methodology to master the migration process at transaction level. This methodology uses some open source tools like SDF3 modified to provide performance estimation at transaction level. These results help the designer to choose the best hardware model in replacement of the previous software implementation of the task object of migration. Using the SDF3 tool, the authors model a multimedia application using SDF graphs. Secondly, they target an MPSoC platform. The authors take a performance constraint to achieve 25 frames per second.


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