Task Migration in Embedded Systems

2013 ◽  
pp. 275-285 ◽  
Author(s):  
Abderrazak Jemai ◽  
Kamel Smiri ◽  
Habib Smei
Keyword(s):  
Embedded Systems ◽  
Performance Estimation ◽  
Design Flow ◽  
Task Migration ◽  
Performance Constraints ◽  
Systems On Chip ◽  
Great Consideration ◽  
Transaction Level ◽  
On Chip ◽  
The Impact

Task migration has a great consideration is MPSoC design and implementation of embedded systems in order to improve performance related to optimizing execution time or reducing energy consumption. Multi-Processor Systems-on-Chip (MPSoC) are now the leading hardware platform featured in embedded systems. This chapter deals with the impact of task migration as an alternative to meet performance constraints in the design flow. The authors explain the different levels of the design process and propose a methodology to master the migration process at transaction level. This methodology uses some open source tools like SDF3 modified to provide performance estimation at transaction level. These results help the designer to choose the best hardware model in replacement of the previous software implementation of the task object of migration. Using the SDF3 tool, the authors model a multimedia application using SDF graphs. Secondly, they target an MPSoC platform. The authors take a performance constraint to achieve 25 frames per second.

Evaluating the impact of task migration in multi-processor systems-on-chip

2010 ◽  
Author(s):  
Gabriel Marchesan Almeida ◽  
Sameer Varyani ◽  
Rémi Busseuil ◽  
Gilles Sassatelli ◽  
Pascal Benoit ◽  
...  
Keyword(s):  
Task Migration ◽  
Systems On Chip ◽  
On Chip ◽  
The Impact

scholarly journals Multilevel MPSoC Performance Evaluation: New ISSPT Model

2015 ◽  
Vol 5 (5) ◽  
pp. 975
Author(s):  
A. Alali ◽  
I. Assayad ◽  
M. Sadik
Keyword(s):  
Performance Evaluation ◽  
High Performance ◽  
Design Space Exploration ◽  
Estimation Error ◽  
Performance Estimation ◽  
Design Flow ◽  
Systems On Chip ◽  
And Performance ◽  
On Chip ◽  
Definition Of

<p>To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin.</p>

SystemC Platform Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems

2010 ◽  
pp. 219-243 ◽  
Author(s):  
Hector Posadas ◽  
Juan Castillo ◽  
David Quijano ◽  
Victor Fernandez ◽  
Eugenio Villar ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Design Space Exploration ◽  
Performance Metrics ◽  
System Modeling ◽  
Performance Estimation ◽  
Behavioral Simulation ◽  
Close Interaction ◽  
Accurate Performance ◽  
And Performance ◽  
On Chip

Currently, embedded systems make use of large, multiprocessing systems on chip integrating complex application software running on the different processors in close interaction with the application-specific hardware. These systems demand new modeling, simulation, and performance estimation tools and methodologies for system architecture evaluation and design exploration. Recently approved as IEEE 1666 standard, SystemC has proven to be a powerful language for system modeling and simulation. In this chapter, SCoPE, a SystemC framework for platform modeling, SW source-code behavioral simulation and performance estimation of embedded systems is presented. Using SCoPE, the application SW running on the different processors of the platform can be simulated efficiently in close interaction with the rest of the platform components. In this way, fast and sufficiently accurate performance metrics are obtained for design-space exploration.

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