Power efficient SDS motion estimation architecture using dynamic iteration control and hierarchical adder compressors for real time HDTV video coding

Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.

Download Full-text

Improvements on Motion Estimation Algorithms in Video Coding for H.264/AVC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.756-759.3455 ◽

2013 ◽

Vol 756-759 ◽

pp. 3455-3460

Author(s):

Xiao Li Wang ◽

Long Zhao

Keyword(s):

Motion Estimation ◽

Video Coding ◽

Real Time ◽

Video Compression ◽

Motion Vector ◽

Coding Efficiency ◽

Estimation Algorithms ◽

Whole Process ◽

Motion Activity ◽

Precision Motion

Motion estimation is the most important step in video compression. By using high precision motion vector in the H.264 encoder, the calculation is rapidly increased, but in the whole process of coding, motion estimation occupies about 80%. Although many motion estimation algorithms have been proposed to reduce the computational complexity of motion estimation, it still cannot meet the strict real-time demand. In this paper, based on the analysis of UMHexagonS algorithm, dynamic searching window is chosen in the UMHexagonS algorithm, then according to the motion activity, it uses different template to reduce the motion estimation time and improve video coding efficiency. Proved by the experiments on various test sequences, compared with the UMHexagonS algorithm, the motion estimation time of the proposed algorithm average saves 17.7525% in the case of the quality of the reconstructed image and rate close. It not only reduces the complexity of the algorithm, but also improves the real-time performance of the encoder.

Download Full-text

Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding

2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics ◽

10.1109/socc.2005.1554465 ◽

2005 ◽

Cited By ~ 2

Author(s):

T. Dias ◽

N. Roma ◽

L. Sousa

Keyword(s):

Motion Estimation ◽

Video Coding ◽

Real Time ◽

Vlsi Architecture ◽

Time Motion ◽

Advanced Video Coding

Download Full-text