scholarly journals Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

2010 ◽  
Vol 34 (7-8) ◽  
pp. 316-328 ◽  
Author(s):  
Sergio Saponara ◽  
Maurizio Martina ◽  
Michele Casula ◽  
Luca Fanucci ◽  
Guido Masera
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Real Time ◽  
High Quality

A coprocessor for real-time motion estimation in HD video coding

2010 ◽  
Author(s):  
Huitao Gu ◽  
Shuwei Sun ◽  
Shuming Chen
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Real Time ◽  
Time Motion

High Performance Hierarchical Block-based Motion Estimation for Real-Time Video Coding

1998 ◽  
Vol 4 (1) ◽  
pp. 67-79 ◽  
Author(s):  
Marco Accame ◽  
Francesco G.B. De Natale ◽  
Daniele D. Giusto
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Real Time ◽  
High Performance ◽  
Block Based

scholarly journals Hardware Efficient Architecture with Variable Block Size for Motion Estimation

2016 ◽  
Vol 2016 ◽  
pp. 1-11
Author(s):  
Nehal N. Shah ◽  
Harikrishna Singapuri ◽  
Upena D. Dalal
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Real Time ◽  
Hardware Implementation ◽  
Clock Cycle ◽  
Block Size ◽  
Absolute Difference ◽  
Worst Case ◽  
Scanning Pattern ◽  
Variable Block

Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.

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