Instruction scheduling with k-successor tree for clustered VLIW processors

2013 ◽  
Vol 17 (2) ◽  
pp. 439-458 ◽  
Author(s):  
Xuemeng Zhang ◽  
Hui Wu ◽  
Jingling Xue
Keyword(s):  
Instruction Scheduling ◽  
Vliw Processors

scholarly journals Certified and efficient instruction scheduling: application to interlocked VLIW processors

2020 ◽  
Vol 4 (OOPSLA) ◽  
pp. 1-29
Author(s):  
Cyril Six ◽  
Sylvain Boulmé ◽  
David Monniaux
Keyword(s):  
Instruction Scheduling ◽  
Vliw Processors

scholarly journals JIST: Just-In-Time Scheduling Translation for Parallel Processors

2005 ◽  
Vol 13 (3) ◽  
pp. 239-253 ◽  
Author(s):  
Giovanni Agosta ◽  
Stefano Crespi Reghizzi ◽  
Gerlando Falauto ◽  
Martino Sykora
Keyword(s):  
Virtual Machines ◽  
Instruction Scheduling ◽  
Mobile Systems ◽  
Just In Time ◽  
Vliw Processors ◽  
Java Bytecode ◽  
Time Scheduling ◽  
Application Fields ◽  
The Impact ◽  
Vliw Architectures

The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

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