Background & Objective:
In this paper, a modified pseudo domino configuration has been
proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic
logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published
domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET
technology which is provided by Stanford.
Methods:
The simulation results of the proposed technique are validated for improvement of wide
fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency.
Results:
The proposed configuration is suitable for cascading of the high performance wide fan-in
circuits without any charge sharing.
Conclusion:
The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides
lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement
is 60% as compared to standard domino circuit.
Dynamic Logic of Legal Competences
