A new constant-time parallel algorithm for merging

2018 ◽  
Vol 75 (2) ◽  
pp. 968-983
Author(s):  
Hazem M. Bahig
1993 ◽  
Vol 03 (02) ◽  
pp. 157-164 ◽  
Author(s):  
P. THANGAVEL ◽  
V.P. MUTHUSWAMY

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.


1993 ◽  
Vol 03 (02) ◽  
pp. 171-177 ◽  
Author(s):  
B. PRADEEP ◽  
C. SIVA RAM MURTHY

The task or precedence graph formalism is a practical tool to study algorithm parallelization. Redundancy in such task graphs gives rise to numerous avoidable inter-task dependencies which invariably complicates the process of parallelization. In this paper we present an O(1) time algorithm for the elimination of redundancy in such graphs on Processor Arrays with Reconfigurable Bus Systemusing O(n4) processors, The previous parallel algorithm available in the literature for redundancy elimination in task graphs takes O(n2) time using O(n) processors.


1998 ◽  
Vol 27 (3) ◽  
pp. 668-681 ◽  
Author(s):  
Maxime Crochemore ◽  
Leszek Gasieniec ◽  
Ramesh Hariharan ◽  
S. Muthukrishnan ◽  
Wojciech Rytter

2010 ◽  
Vol 24 (7) ◽  
pp. 638-642
Author(s):  
Linli Cui ◽  
Fan Yang ◽  
Qicong Peng

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