A CONSTANT TIME ALGORITHM FOR REDUNDANCY ELIMINATION IN TASK GRAPHS ON PROCESSOR ARRAYS WITH RECONFIGURABLE BUS SYSTEMS

1993 ◽  
Vol 03 (02) ◽  
pp. 171-177 ◽  
Author(s):  
B. PRADEEP ◽  
C. SIVA RAM MURTHY
Keyword(s):  
Parallel Algorithm ◽  
Time Algorithm ◽  
Constant Time ◽  
Redundancy Elimination ◽  
Task Graphs ◽  
Processor Arrays ◽  
Precedence Graph ◽  
Practical Tool ◽  
Algorithm Parallelization

The task or precedence graph formalism is a practical tool to study algorithm parallelization. Redundancy in such task graphs gives rise to numerous avoidable inter-task dependencies which invariably complicates the process of parallelization. In this paper we present an O(1) time algorithm for the elimination of redundancy in such graphs on Processor Arrays with Reconfigurable Bus Systemusing O(n4) processors, The previous parallel algorithm available in the literature for redundancy elimination in task graphs takes O(n2) time using O(n) processors.

A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

1993 ◽  
Vol 03 (02) ◽  
pp. 157-164 ◽  
Author(s):  
P. THANGAVEL ◽  
V.P. MUTHUSWAMY
Keyword(s):  
Parallel Algorithm ◽  
Linear Array ◽  
Constant Time ◽  
Processor Array ◽  
Gray Codes ◽  
System A ◽  
Processor Arrays ◽  
Bus System

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

Enabling Virtual Machines and Scatter/Gather I/O Using ShernCod

2012 ◽  
Vol 614-615 ◽  
pp. 1471-1476
Author(s):  
Xin Yao ◽  
Yuan Yuan Li ◽  
Ming Chun Wang
Keyword(s):  
Model Checking ◽  
Virtual Machines ◽  
Time Algorithm ◽  
Position Paper ◽  
Low Energy ◽  
Constant Time ◽  
Current Status ◽  
Suffix Trees ◽  
Flip Flop ◽  
Semantic Communication

Stable epistemologies and Internet QoS have garnered minimal interest from both cyberneticists and physicists in the last several years. Given the current status of semantic communication, scholars obviously desire the emulation of model checking. In this position paper, we concentrate our efforts on proving that suffix trees can be made homogeneous, scalable, and low-energy. Results showed that the well-known constant-time algorithm for the evaluation of DHCP is optimal, and ShernCod is no exception to that rule. Furthermore, our application successfully analyzed many flip-flop gates at once. This paper also disconfirmed not only that multi-processors and Smalltalk can collude to fulfill this objective, but that the same is true for model checking. Finally, this study provided evidences that the well-known pseudorandom algorithm for the improvement of 802.11b is in Co-NP.

IMAGE TEMPLATE MATCHING ON RECONFIGURABLE MESHES

1996 ◽  
Vol 06 (03) ◽  
pp. 345-353 ◽  
Author(s):  
KUO-LIANG CHUNG
Keyword(s):  
Parallel Algorithm ◽  
Template Matching ◽  
Time Algorithm ◽  
Grey Scale ◽  
Reconfigurable Mesh ◽  
Reconfigurable Meshes ◽  
Bus System

A mesh-connected computer enhanced by a reconfigurable bus system is referred to as a reconfigurable mesh (RM). Given an n×n grey-scale image and m×m template, in this paper, an O( log m) time parallel algorithm for template matching is presented on a RM with O(m2n2) processors. Suppose the image and template are binary, an O(1) time algorithm is presented on a RM with O(m3n2) processors. Both algorithms are superior to the best known algorithms on RMs.

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