Error-tolerance pooling designs based on Johnson graphs

2012 ◽  
Vol 8 (3) ◽  
pp. 1161-1165 ◽  
Author(s):  
Benjian Lv ◽  
Kaishun Wang ◽  
Jun Guo
Keyword(s):  
Error Tolerance ◽  
Pooling Designs ◽  
Johnson Graphs

scholarly journals New constructions of non-adaptive and error-tolerance pooling designs

2002 ◽  
Vol 243 (1-3) ◽  
pp. 161-170 ◽  
Author(s):  
Hung Q. Ngo ◽  
Ding-Zhu Du
Keyword(s):  
Error Tolerance ◽  
Pooling Designs

scholarly journals Improvements on some error-tolerance pooling designs

2016 ◽  
Vol 200 ◽  
pp. 18-22
Author(s):  
Huilan Chang ◽  
Yi-Tsz Tsai
Keyword(s):  
Error Tolerance ◽  
Pooling Designs

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

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