scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-12
Author(s):  
Dave Y.-W. Lin ◽  
Charles H.-P. Wen
Keyword(s):  
Energy Levels ◽  
Soft Error ◽  
Test Method ◽  
Experimental Result ◽  
Flip Flop ◽  
Area Overhead ◽  
Design Reliability ◽  
Radiation Hardened ◽  
Self Test ◽  
Built In Self Test

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

scholarly journals Single-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains

2011 ◽  
Vol 58 (6) ◽  
pp. 2695-2701 ◽  
Author(s):  
Paul E. Dodd ◽  
Marty R. Shaneyfelt ◽  
Richard S. Flores ◽  
James R. Schwank ◽  
Thomas A. Hill ◽  
...  
Keyword(s):  
Single Event ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Radiation Hardened

Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits

2018 ◽  
Vol 27 (06) ◽  
pp. 1850097 ◽  
Author(s):  
Ahmad T. Sheikh ◽  
Aiman H. El-Maleh
Keyword(s):  
System Reliability ◽  
High Reliability ◽  
Soft Error ◽  
Error Tolerance ◽  
Digital Systems ◽  
Combinational Circuits ◽  
Power Devices ◽  
Area Overhead ◽  
Modular Redundancy ◽  
Increased Susceptibility

Due to the continuous scaling of digital systems and the increased demand on low power devices, design of effective soft error tolerance techniques is of high importance to cope with the increased susceptibility of systems to soft errors and to enhance system reliability. In this work, we propose a double modular redundancy (DMR) technique that aims to achieve high reliability with reduced area overhead. Furthermore, we propose an improved application of DMR based on the use of C-element (DMR-CEL). The proposed technique is compared with Triple Modular Redundancy (TMR) technique and DMR-CEL. Simulations performed for LGSynth’91 benchmark circuits demonstrate that applying the proposed DMR technique achieves improved reliability with significantly lower area overhead than TMR without voter protection. Furthermore, improved reliability with lower area overhead is achieved by the proposed DMR technique in comparison to DMR-CEL without C-element protection. In addition, applying a recently proposed transistor sizing technique on our proposed DMR technique achieves comparable reliability to that achieved by TMR with voter protection and DMR-CEL with C-element protection with lower area overhead than TMR.

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