An analytical model for Network-on-Chip with finite input buffer

Jian Wang; Yu-bai Li; Chang Wu

doi:10.1007/s11704-010-0117-0

An analytical model for Network-on-Chip with finite input buffer

Frontiers of Computer Science in China ◽

10.1007/s11704-010-0117-0 ◽

2010 ◽

Vol 5 (1) ◽

pp. 126-134 ◽

Cited By ~ 4

Author(s):

Jian Wang ◽

Yu-bai Li ◽

Chang Wu

Keyword(s):

Analytical Model ◽

Network On Chip ◽

Input Buffer ◽

On Chip

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An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip

2007 IEEE International Conference on Integration Technology ◽

10.1109/icitechnology.2007.4290470 ◽

2007 ◽

Author(s):

Kun Huang ◽

Jun Wang ◽

Ge Zhang

Keyword(s):

Network On Chip ◽

Input Buffer ◽

Power Efficient ◽

On Chip

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An analytical model for segmented bus enhanced network on chip

2017 7th International Conference on Computer and Knowledge Engineering (ICCKE) ◽

10.1109/iccke.2017.8167932 ◽

2017 ◽

Author(s):

Hossein Bastan ◽

Mohammad Ali Montazeri ◽

Amin Ghalami Osgouei ◽

Amir Khorsandi ◽

Hossein Saidi

Keyword(s):

Analytical Model ◽

Network On Chip ◽

On Chip

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A Novel Analytical Model for Network-on-Chip using Semi-Markov Process

Advances in Electrical and Computer Engineering ◽

10.4316/aece.2011.01018 ◽

2011 ◽

Vol 11 (1) ◽

pp. 111-118 ◽

Cited By ~ 2

Author(s):

J. WANG ◽

Y. LI ◽

Q. PENG

Keyword(s):

Markov Process ◽

Analytical Model ◽

Network On Chip ◽

Semi Markov Process ◽

On Chip

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Input buffer planning for network-on-chip router design

2010 International Conference on Computer Application and System Modeling (ICCASM 2010) ◽

10.1109/iccasm.2010.5622722 ◽

2010 ◽

Cited By ~ 1

Author(s):

Yaming Yin ◽

Shuming Chen ◽

Xiao Hu

Keyword(s):

Network On Chip ◽

Input Buffer ◽

Buffer Planning ◽

On Chip

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A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2017.2736004 ◽

2017 ◽

Vol 25 (11) ◽

pp. 3099-3112 ◽

Cited By ~ 3

Author(s):

Khanh N. Dang ◽

Akram Ben Ahmed ◽

Xuan-Tu Tran ◽

Yuichi Okuyama ◽

Abderazek Ben Abdallah

Keyword(s):

Analytical Model ◽

Reliability Assessment ◽

Network On Chip ◽

On Chip ◽

Comprehensive Reliability

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A novel analytical model for wormhole switching network on chip with adaptive routing

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548715 ◽

2010 ◽

Cited By ~ 1

Author(s):

Jin Liu ◽

Jose G. Delgado-Frias ◽

Xiaofeng Wang

Keyword(s):

Analytical Model ◽

Adaptive Routing ◽

Network On Chip ◽

Switching Network ◽

Wormhole Switching ◽

On Chip

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A performance analytical model for Network-on-Chip with constant service time routers

Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09 ◽

10.1145/1687399.1687506 ◽

2009 ◽

Cited By ~ 22

Author(s):

Nikita Nikitin ◽

Jordi Cortadella

Keyword(s):

Analytical Model ◽

Service Time ◽

Network On Chip ◽

On Chip ◽

A Performance

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A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

Advances in Electrical and Computer Engineering ◽

10.4316/aece.2012.04003 ◽

2012 ◽

Vol 12 (4) ◽

pp. 19-24 ◽

Cited By ~ 1

Author(s):

J. WANG ◽

Y. LI ◽

H. LI

Keyword(s):

Network On Chip ◽

Input Buffer ◽

Analytical Strategy ◽

On Chip ◽

A Performance

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

On Chip

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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