Input buffer planning for network-on-chip router design

2010 ◽  
Author(s):  
Yaming Yin ◽  
Shuming Chen ◽  
Xiao Hu
Keyword(s):  
Network On Chip ◽  
Input Buffer ◽  
Buffer Planning ◽  
On Chip

An analytical model for Network-on-Chip with finite input buffer

2010 ◽  
Vol 5 (1) ◽  
pp. 126-134 ◽  
Author(s):  
Jian Wang ◽  
Yu-bai Li ◽  
Chang Wu
Keyword(s):  
Analytical Model ◽  
Network On Chip ◽  
Input Buffer ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document