Background:
In the field of IC physical design, there is a big problem in the IC floorplanning
to find the early feedback to estimate the area, wire length, delay, etc. before IC fabrication.
Objective:
In this paper, minimization of the area and total wire length on the IC has been done using
Binary Particle Swarm Optimization with sequence pair representation.
Methods:
Optimization of the IC floorplan works in two phases. In the first phase, the floorplan is
constructed by sequence pair representation without any overlapping of the modules on IC floorplan.
In the second phase, Binary Particle Swarm Optimization algorithm explores the packing of all
modules in floorplan to find better optimal performances i.e. area and wire length.
Results:
The results obtained were compared with the solutions derived from other meta-heuristic
algorithms, the area is improved maximum up to 10% and the wire length was improved maximum
up to 28%.
Conclusion:
The Experimental results on Microelectronic Center of North Carolina benchmark circuits
show that Binary Particle Swarm Optimization algorithm gives better convergence for the area
and wire length optimization than other algorithms.
Nodes selection mechanism based on modified binary particle swarm optimization algorithm
