Thermal stability of fission tracks in apatite and sphene: Using confined-track-length measurements

1985 ◽  
Vol 10 (3) ◽  
pp. 349-357 ◽  
Author(s):  
S. Watt ◽  
S.A. Durrani
1995 ◽  
Vol 24 (2) ◽  
pp. 169-170
Author(s):  
G. Bigazzi ◽  
J.C. Hadler Neto ◽  
M.Khouri Cesar ◽  
A.M. Osorio Araya

Geochronology ◽  
2021 ◽  
Vol 3 (2) ◽  
pp. 433-464
Author(s):  
Richard A. Ketcham ◽  
Murat T. Tamer

Abstract. We present a new model for the etching and revelation of confined fission tracks in apatite based on variable along-track etching velocity, vT(x). Insights from step-etching experiments and theoretical energy loss rates of fission fragments suggest two end-member etching structures: constant-core, with a central zone of constant etching rate that then falls off toward track tips; and linear, in which etching rates fall linearly from the midpoint to the tips. From these, we construct a characterization of confined track revelation that encompasses all relevant processes, including penetration and widening of semi-tracks etching in from the polished grain surface, intersection with and expansion of confined tracks, and analyst selection of which tracks to measure and which to bypass. Both etching structures are able to fit step-etching data from five sets of paired experiments of fossil tracks and unannealed and annealed induced tracks in Durango apatite, supporting the correctness of our approach and providing a series of insights into the theory and practice of fission-track thermochronology. Etching rates for annealed induced tracks are much faster than those for unannealed induced and spontaneous tracks, impacting the relative efficiency of both confined track length and density measurements and suggesting that high-temperature laboratory annealing may induce a transformation in track cores that does not occur at geological conditions of partial annealing. The model quantifies how variation in analyst selection criteria, summarized as the ratio of along-track to bulk etching velocity at the etched track tip (vT/vB), likely plays a first-order role in the reproducibility of confined length measurements. It also accounts for and provides an estimate of the large proportion of tracks that are intersected but not measured, and it shows how length biasing is likely to be an insufficient basis for predicting the relative probability of detection of different track populations. The vT(x) model provides an approach to optimizing etching conditions, linking track length measurements across etching protocols, and discerning new information on the underlying structure of fission tracks.


Author(s):  
Shiro Fujishiro ◽  
Harold L. Gegel

Ordered-alpha titanium alloys having a DO19 type structure have good potential for high temperature (600°C) applications, due to the thermal stability of the ordered phase and the inherent resistance to recrystallization of these alloys. Five different Ti-Al-Ga alloys consisting of equal atomic percents of aluminum and gallium solute additions up to the stoichiometric composition, Ti3(Al, Ga), were used to study the growth kinetics of the ordered phase and the nature of its interface.The alloys were homogenized in the beta region in a vacuum of about 5×10-7 torr, furnace cooled; reheated in air to 50°C below the alpha transus for hot working. The alloys were subsequently acid cleaned, annealed in vacuo, and cold rolled to about. 050 inch prior to additional homogenization


Author(s):  
Yih-Cheng Shih ◽  
E. L. Wilkie

Tungsten silicides (WSix) have been successfully used as the gate materials in self-aligned GaAs metal-semiconductor-field- effect transistors (MESFET). Thermal stability of the WSix/GaAs Schottky contact is of major concern since the n+ implanted source/drain regions must be annealed at high temperatures (∼ 800°C). WSi0.6 was considered the best composition to achieve good device performance due to its low stress and excellent thermal stability of the WSix/GaAs interface. The film adhesion and the uniformity in barrier heights and ideality factors of the WSi0.6 films have been improved by depositing a thin layer of pure W as the first layer on GaAs prior to WSi0.6 deposition. Recently WSi0.1 has been used successfully as the gate material in 1x10 μm GaAs FET's on the GaAs substrates which were sputter-cleaned prior to deposition. These GaAs FET's exhibited uniform threshold voltages across a 51 mm wafer with good film adhesion after annealing at 800°C for 10 min.


1991 ◽  
Vol 1 (12) ◽  
pp. 1823-1836 ◽  
Author(s):  
M. Bessière ◽  
A. Quivy ◽  
S. Lefebvre ◽  
J. Devaud-Rzepski ◽  
Y. Calvayrac

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