Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

High-k Fluoropolymers Dielectrics for Low-Bias Ambipolar Organic Light Emitting Transistors (OLETs)

Organic light emitting transistors (OLETs) combine, in the same device, the function of an electrical switch with the capability of generating light under appropriate bias conditions. In this work, we demonstrate how engineering the dielectric layer based on high-k polyvinylidene fluoride (PVDF)-based polymers can lead to a drastic reduction of device driving voltages and the improvement of its optoelectronic properties. We first investigated the morphology and the dielectric response of these polymer dielectrics in terms of polymer (P(VDF-TrFE) and P(VDF-TrFE-CFE)) and solvent content (cyclopentanone, methylethylketone). Implementing these high-k PVDF-based dielectrics enabled low-bias ambipolar organic light emitting transistors, with reduced threshold voltages (<20 V) and enhanced light output (compared to conventional polymer reference), along with an overall improvement of the device efficiency. Further, we preliminary transferred these fluorinated high-k dielectric films onto a plastic substrate to enable flexible light emitting transistors. These findings hold potential for broader exploitation of the OLET platform, where the device can now be driven by commercially available electronics, thus enabling flexible low-bias organic electronic devices.

ZnO nanowires and their application in field-effect transistors

<p>ZnO nanowires have shown great promise as a semiconducting material for a variety of different electronic applications at the nanoscale, and can be easily synthesised at low temperatures using the hydrothermal growth method. However, efforts to reliably produce field-effect transistors (FETs) using ZnO nanowires have been hampered by excessive charge carriers, requiring high temperature annealing (≥400°C) at the expense of the low-temperature synthesis before field dependence is achieved. This thesis presents hydrothermally synthesised ZnO nanowires which can effectively be used as FETs in dry and liquid environments without requiring any annealing or post-growth processing. The role of polyethylenimine (PEI) in the hydrothermal growth of vertical ZnO nanowires is thoroughly investigated. PEI is a polymer used to increase the aspect ratio of ZnO nanowires, but the molecular weight of the polymer and interactions with other growth precursors are often overlooked. Using 4 mM of PEI(MW = 1300 g/mol) results in hierarchical nanowires, consisting of large primary nanowires which abruptly terminate in thinner secondary nanowires. The secondary nanowires, with lengths of up to 10 m and diameters below 50 nm, are synthesised during a PEI-mediated secondary growth phase, where Zn-PEI complexes continue to provide Zn²⁺ ions after the bulk of the precursors have been exhausted. The PEI-mediated synthesis of hierarchical nanowires is used to fabricate FETs by laterally growing intersecting networks of nanowires from spaced pairs of ZnO/Ti films, which have been patterned on SiO₂/Si device substrates. All of these FETs show marked field dependence between VG = -10 V to 10 V, despite being used without annealing. Typical on-off ratios are between 10³ - 10⁵, with threshold voltages between -7.5 V to 5 V. This is a significant result, as the majority of ZnO nanowire FETs reported in the literature require high temperature annealing. Persistent photoconductivity measurements indicate that surface states on the nanowires contribute to the intrinsic field dependence of the devices. Hierarchical nanowires are also synthesised by modular primary and secondary hydrothermal growths. FETs fabricated using these hierarchical nanowires show less field dependence than PEI-mediated hierarchical nanowires, with limited function ality when used in air. The best FET measured in air operates with an on-off ratio of 10⁴ and a threshold voltage of ~ 0 V. Devices which are field-independent in air can be reliably gated by measuring the FETs in a wet environment, using de-ionised water as a dielectric. A back-gated wet FET operates with an on-off ratio of 105 and a threshold voltage of ~ 8 V. Top-gated wet FETs operate with on-off ratios within 103 - 104, and threshold voltages within 0.4 - 0.9 V. These devices also have significantly low subthreshold swings, on the order of 80 mV/decade. FETs are fabricated by contacting individual ZnO nanowires using electron-beam lithography, although only one vertical ZnO nanowire shows field dependence, with an on-off ratio of 10⁴ and a threshold voltage of -7 V. A PEI-mediated hierarchical nanowire is also contacted and shows field dependence, with an on-off ratio of 10² and a threshold voltage of -6 V. The poor on-off ratio is caused by high leakage currents of the device. The contacted nanowires undergo dissolution over time, disappearing from the substrates after 8 months, and also exhibit a conducting-to-insulating transition over 48 hours. This transition can be temporarily reversed by exposure to an electron beam. Neither of these effects are reported in the literature, and their causes are speculated on. Finally, the thesis concludes with proposals for future work to further the advances made here.</p>

ZnO nanowires and their application in field-effect transistors

<p>ZnO nanowires have shown great promise as a semiconducting material for a variety of different electronic applications at the nanoscale, and can be easily synthesised at low temperatures using the hydrothermal growth method. However, efforts to reliably produce field-effect transistors (FETs) using ZnO nanowires have been hampered by excessive charge carriers, requiring high temperature annealing (≥400°C) at the expense of the low-temperature synthesis before field dependence is achieved. This thesis presents hydrothermally synthesised ZnO nanowires which can effectively be used as FETs in dry and liquid environments without requiring any annealing or post-growth processing. The role of polyethylenimine (PEI) in the hydrothermal growth of vertical ZnO nanowires is thoroughly investigated. PEI is a polymer used to increase the aspect ratio of ZnO nanowires, but the molecular weight of the polymer and interactions with other growth precursors are often overlooked. Using 4 mM of PEI(MW = 1300 g/mol) results in hierarchical nanowires, consisting of large primary nanowires which abruptly terminate in thinner secondary nanowires. The secondary nanowires, with lengths of up to 10 m and diameters below 50 nm, are synthesised during a PEI-mediated secondary growth phase, where Zn-PEI complexes continue to provide Zn²⁺ ions after the bulk of the precursors have been exhausted. The PEI-mediated synthesis of hierarchical nanowires is used to fabricate FETs by laterally growing intersecting networks of nanowires from spaced pairs of ZnO/Ti films, which have been patterned on SiO₂/Si device substrates. All of these FETs show marked field dependence between VG = -10 V to 10 V, despite being used without annealing. Typical on-off ratios are between 10³ - 10⁵, with threshold voltages between -7.5 V to 5 V. This is a significant result, as the majority of ZnO nanowire FETs reported in the literature require high temperature annealing. Persistent photoconductivity measurements indicate that surface states on the nanowires contribute to the intrinsic field dependence of the devices. Hierarchical nanowires are also synthesised by modular primary and secondary hydrothermal growths. FETs fabricated using these hierarchical nanowires show less field dependence than PEI-mediated hierarchical nanowires, with limited function ality when used in air. The best FET measured in air operates with an on-off ratio of 10⁴ and a threshold voltage of ~ 0 V. Devices which are field-independent in air can be reliably gated by measuring the FETs in a wet environment, using de-ionised water as a dielectric. A back-gated wet FET operates with an on-off ratio of 105 and a threshold voltage of ~ 8 V. Top-gated wet FETs operate with on-off ratios within 103 - 104, and threshold voltages within 0.4 - 0.9 V. These devices also have significantly low subthreshold swings, on the order of 80 mV/decade. FETs are fabricated by contacting individual ZnO nanowires using electron-beam lithography, although only one vertical ZnO nanowire shows field dependence, with an on-off ratio of 10⁴ and a threshold voltage of -7 V. A PEI-mediated hierarchical nanowire is also contacted and shows field dependence, with an on-off ratio of 10² and a threshold voltage of -6 V. The poor on-off ratio is caused by high leakage currents of the device. The contacted nanowires undergo dissolution over time, disappearing from the substrates after 8 months, and also exhibit a conducting-to-insulating transition over 48 hours. This transition can be temporarily reversed by exposure to an electron beam. Neither of these effects are reported in the literature, and their causes are speculated on. Finally, the thesis concludes with proposals for future work to further the advances made here.</p>

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages (VTH). The results show that VTH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. VTH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive VGS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to VGS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the VTH shift, thereby indicating thermal acceleration of negative charge trapping. VTH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of VGS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions.

Read Reference Calibration and Tracking for Non-Volatile Flash Memories

The performance and reliability of nonvolatile NAND flash memories deteriorate as the number of program/erase cycles grows. The reliability also suffers from cell-to-cell interference, long data retention time, and read disturb. These processes effect the read threshold voltages. The aging of the cells causes voltage shifts which lead to high bit error rates (BER) with fixed predefined read thresholds. This work proposes two methods that aim on minimizing the BER by adjusting the read thresholds. Both methods utilize the number of errors detected in the codeword of an error correction code. It is demonstrated that the observed number of errors is a good measure for the voltage shifts and is utilized for the initial calibration of the read thresholds. The second approach is a gradual channel estimation method that utilizes the asymmetrical error probabilities for the one-to-zero and zero-to-one errors that are caused by threshold calibration errors. Both methods are investigated utilizing the mutual information between the optimal read voltage and the measured error values. Numerical results obtained from flash measurements show that these methods reduce the BER of NAND flash memories significantly.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Effect of Ge Mole Fraction on Performance of Underlapped Gate-All-Around SiGe-Source Tunneling Field-Effect Transistors

In this paper, we propose the design optimization of underlapped Si1–xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I–V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1–xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

Illumination Effect on Electrical Characteristics of Poly(3-hexylthiophene): TIPS-Pentacene Blend Thin-Film Transistor

Organic phototransistors capable of absorbing in the visible light spectrum without color filters are the best alternatives to conventional inorganic phototransistors. In this study, the effect of illumination on the electrical characteristics of a solution-processed poly(3-hexylthiophene): 6,13-bis(triisopropylsilylethynyl) pentacene-blend thin-film transistor (TFT) was investigated. The wavelengths of the irradiated light were determined from the absorbance spectrum of the blended film and changes in the transistor’s electrical characteristics were explained in relation to the electrical and light absorption properties of each component material. The photosensitivity and absorbing properties of the blended TFT were enhanced at 515 and 450 nm and exhibited positively shifted threshold voltages under incident light. The results indicated that the photo-generated exci-ton pair characteristics matched the absorbance properties of the blended material and that the absorption and photocurrent characteristics of the respective components could be combined. This process for the heterogeneous blending of organic semiconductors has the potential to improve phototransistor performance and contribute to the development of broadband absorbing phototransistors.

A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).