Characterizing the conformational free-energy landscape of RNA using single-molecule field-effect transistors

We have developed and used high-time-resolution, single-molecule field-effect transistors (smFETs) to characterize the con-formational free-energy landscape of RNA stem-loops. Stem-loops are some of the most common RNA structural motifs and serve as building blocks for the formation of more complex RNA structures. Given their prevalence and integral role in RNA folding, the kinetics of stem-loop (un)folding has been extensively characterized using both experimental and computational approaches. Interestingly, these studies have reported vastly disparate timescales of (un)folding, which has been recently in-terpreted as evidence that (un)folding of even simple stem-loops occurs on a highly rugged conformational energy landscape. Because smFETs do not rely on fluorophore reporters of conformation or on the application of mechanical (un)folding forces, they provide a unique and complementary approach that has allowed us to directly monitor tens of thousands of (un)folding events of individual stem-loops at a 200 μs time resolution. Our results show that under our experimental conditions, stem-loops fold and unfold over a 1-200 ms timescale during which they transition between ensembles of unfolded and folded conformations, the latter of which is composed of at least two sub-populations. The 1-200 ms timescale of (un)folding we observe here indicates that smFETs report on complete (un)folding trajectories in which relatively extended unfolded con-formations of the RNA spend long periods of time wandering the free-energy landscape before sampling one of several mis-folded conformations or, alternatively, the natively folded conformation. Our findings demonstrate how the combination of single-molecule sensitivity and high time resolution makes smFETs unique and powerful tools for characterizing the con-formational free-energy landscape of RNA and highlight the extremely rugged landscape on which even the simplest RNA structural elements fold.

Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

High drain-current-density and high breakdown-field Al0.36Ga0.64N-channel heterojunction filed-effect transistors with a dual AlN/AlGaInN barrier layer

In this study, we fabricated and characterized heterojunction field-effect transistors (HFETs) based on an Al0.36Ga0.64N-channel heterostructure with a dual AlN/AlGaInN barrier layer. The device fabrication was accomplished by adopting a regrown n++-GaN layer for ohmic contacts. The fabricated HFETs with a gate length of 2 μm and a gate-to-drain distance of 6 μm exhibited an on-state drain current density as high as approximately 270 mA/mm and an off-state breakdown voltage of approximately 1 kV, which corresponds to an off-state critical electric field of 166 V/μm. This breakdown field, as a comparison in devices without field-plate electrodes, reaches approximately four-fold higher than that for conventional GaN-channel HFETs and was considered quite reasonable as an Al0.36Ga0.64N-channel transistor. It was also confirmed that the devices adopting the dual AlN/AlGaInN barrier layer showed approximately one order of magnitude smaller gate leakage currents than those for devices without the top AlN barrier layer.

Emerging Internet of Things driven carbon nanotubes-based devices

Carbon nanotubes (CNTs) have attracted great attentions in the field of electronics, sensors, healthcare, and energy conversion. Such emerging applications have driven the carbon nanotube research in a rapid fashion. Indeed, the structure control over CNTs has inspired an intensive research vortex due to the high promises in electronic and optical device applications. Here, this in-depth review is anticipated to provide insights into the controllable synthesis and applications of high-quality CNTs. First, the general synthesis and post-purification of CNTs are briefly discussed. Then, the state-of-the-art electronic device applications are discussed, including field-effect transistors, gas sensors, DNA biosensors, and pressure gauges. Besides, the optical sensors are delivered based on the photoluminescence. In addition, energy applications of CNTs are discussed such as thermoelectric energy generators. Eventually, future opportunities are proposed for the Internet of Things (IoT) oriented sensors, data processing, and artificial intelligence.

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.