2009 ◽  
Vol 48 (4) ◽  
pp. 2245-2256 ◽  
Author(s):  
Charles C. Solvason ◽  
Nishanth G. Chemmangattuvalappil ◽  
Fadwa T. Eljack ◽  
Mario R. Eden

2005 ◽  
Vol 29 (11-12) ◽  
pp. 2304-2317 ◽  
Author(s):  
Fadwa T. Eljack ◽  
Ahmed F. Abdelhady ◽  
Mario R. Eden ◽  
Frederico B. Gabriel ◽  
Xiaoyun Qin ◽  
...  

2007 ◽  
Vol 46 (10) ◽  
pp. 3400-3409 ◽  
Author(s):  
Vasiliki Kazantzi ◽  
Xiaoyun Qin ◽  
Mahmoud El-Halwagi ◽  
Fadwa Eljack ◽  
Mario Eden

2020 ◽  
Author(s):  
Andrea Giani ◽  
de Souza Patricia Borges ◽  
Stefania Bartoletti ◽  
Flavio Morselli ◽  
Andrea Conti ◽  
...  

2019 ◽  
Vol 7 (3) ◽  
pp. 50-54
Author(s):  
N. Thilagavathi ◽  
Christy Wood ◽  
V. Hemalakshumi ◽  
V. Mathumiithaa

Author(s):  
Wing Chiu Tam ◽  
Osei Poku ◽  
R. D. (Shawn) Blanton

Abstract Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.


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