Systematic Defect Identification through Layout Snippet Clustering

2010 ◽  
Author(s):  
Wing Chiu Tam ◽  
Osei Poku ◽  
R. D. (Shawn) Blanton
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Yield Loss ◽  
Defect Identification ◽  
Clustering Techniques ◽  
Dominant Component

Abstract Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

DoD Design Cloud Analysis: Securing the Integrated Circuit Design Process

2012 ◽  
Author(s):  
Mario N. Gomez
Keyword(s):  
At Risk ◽  
Design Process ◽  
Circuit Design ◽  
Department Of Defense ◽  
Integrated Circuit ◽  
Secure Communication ◽  
Integrated Circuit Design ◽  
Defense Systems ◽  
Design Software ◽  
Security Costs

The use of unsecure foundries has allowed and is still providing a pathway for counterfeit microelectronics into U.S. defense systems. As a result, the Warfighter has been put at risk and a solution is needed. To counter this dilemma, this study looks into the feasibility of creating a Department of Defense (DoD) - wide design cloud that would provide circuit designers with a more secure and economical way of designing and fabricating circuits. The design cloud would include secure communication to trusted foundries along with needed circuit design software. Factors such as security, costs, benefits, and issues are taken into consideration in determining whether the use of the cloud would actually aid the integrated circuit design process.

scholarly journals Basic Consecutive System Consisted of Design, Process and Estimation of a Fundamental Integrated Circuit Education System

2008 ◽  
Vol 128 (11) ◽  
pp. 683-688 ◽  
Author(s):  
Hiroyuki Kataoka ◽  
Akihiro Yamada ◽  
Hiroki Kamizono ◽  
Hideyuki Ando ◽  
Takeshi Tanaka
Keyword(s):  
Design Process ◽  
Education System ◽  
Integrated Circuit ◽  
Consecutive System

A Lion’s Pride Inspired Algorithm for VLSI Floorplanning

2019 ◽  
Vol 29 (01) ◽  
pp. 2050003
Author(s):  
Lalin L. Laudis ◽  
N. Ramadass
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Large Scale ◽  
Optimization Problem ◽  
Standard Test ◽  
Test Problems ◽  
Multi Objective Optimization ◽  
Multi Objective ◽  
Scale Integration ◽  
Vlsi Floorplanning

The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.

scholarly journals Modeling of integrated circuit yield loss mechanisms

1996 ◽  
Vol 9 (2) ◽  
pp. 270-272 ◽  
Author(s):  
Z. Stamenkovic ◽  
N. Stojadinovic ◽  
S. Dimitrijev
Keyword(s):  
Integrated Circuit ◽  
Yield Loss ◽  
Circuit Yield ◽  
Loss Mechanisms

scholarly journals MECHANICAL APPROACH AS ERROR PROOFING TO PREVENT WRONG ORIENTATION OF PRODUCT

2016 ◽  
Vol 5 (3) ◽  
Author(s):  
Arif Rahman Hakim
Keyword(s):  
Design Process ◽  
Error Detection ◽  
Integrated Circuit ◽  
Raw Material ◽  
Working Process ◽  
Mechanical Approach ◽  
Human Capability ◽  
Post Production ◽  
Production Part ◽  
Error Proofing

Error or mistake is occurred in such away that causing product malfunction, machine not working, process produce defective. All of these affect the quality and productivity, further more will increase cost of production.Many aspects can create error, such as human, design, process, raw material, method and environment. A lot of effort put in place to prevent or eliminate error. Detection by inspection is old method applied in industry. Detection can be applied pre production or post production. Both of method has their own advantages. Inspection prior production will ensure the input are free from defect, while inspection post production is to prevent defect escape to customer.In many industries nowdays, inspection still being carried out by human. This type of inspection has been affected by human capability which is very hard to be consistent at all time. In Integrated Circuit Assembly manufacturing, some problem may happen due to wrong orientation and or misalignment of production part. This research is carried out in one of IC assembly manufacture in Batam. 

Photo-Induced Corrosion in Microelectronic Devices Containing Dissimilar Metals.

2003 ◽  
Vol 781 ◽  
Author(s):  
C. Belisle ◽  
L. Westergard ◽  
D. Florence ◽  
T. Haskett ◽  
G. Scott ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Yield Loss ◽  
Galvanic Corrosion ◽  
Dissimilar Metals ◽  
Integrated Circuit Manufacturing ◽  
Microelectronic Devices ◽  
Metal Levels ◽  
Tungsten Metal ◽  
Metal Layers ◽  
Microelectronic Manufacturing

AbstractVarious metals with different galvanic potentials are used to fabricate the microelectronic circuits. One of the most commonly used processes during integrated circuit manufacturing is the tungsten via fill. To obtain maximum interconnect density with low via resistance requires that metal-via overlap is essentially zero. Zero overlap with litho variations and thus misalignment may result in unlanded vias. Since the vias are used to connect various metal levels, a large number of these cases may occur causing device failures and thus yield loss. To study this problem a variety of test structures were studied and a new mechanism of corrosion was found. The tungsten corrosion observed in these structures was found to be photo-induced. In this paper we will discuss the mechanism of photoinduced galvanic corrosion that occurs between the aluminum and tungsten metal layers during microelectronic manufacturing.

The ASIC Design and Verification Based on Verilog HDL

2012 ◽  
Vol 433-440 ◽  
pp. 4578-4583
Author(s):  
Yu Ying Yuan ◽  
Yong Gang Luo
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Logic Design ◽  
Verilog Hdl ◽  
Asic Design ◽  
Application Specific Integrated Circuit ◽  
Design Requirements ◽  
Cross Connect ◽  
Application Specific ◽  
Important Design

Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.

Sign in / Sign up

Export Citation Format

Share Document