Hardware Implementation of Data Compression

2003 ◽  
pp. 405-446 ◽  
Author(s):  
Sanjukta Bhanja ◽  
N. Ranganathan
Keyword(s):  
Data Compression ◽  
Hardware Implementation

A Hardware Implementation of Real Time Lossless Data Compression and Decompression Circuits

2015 ◽  
Vol 719-720 ◽  
pp. 554-560
Author(s):  
Le Yang ◽  
Zhao Yang Guo ◽  
Shan Shan Yong ◽  
Feng Guo ◽  
Xin An Wang
Keyword(s):  
Data Compression ◽  
Real Time ◽  
Hardware Implementation ◽  
Storage Capacity ◽  
Time Data ◽  
Hardware Resource ◽  
Hardware Description ◽  
Lossless Data Compression ◽  
Timing Simulation ◽  
Lzw Algorithm

This paper presents a hardware implementation of real time data compression and decompression circuits based on the LZW algorithm. LZW is a dictionary based data compression, which has the advantage of fast speed, high compression, and small resource occupation. In compression circuit, the design creatively utilizes two dictionaries alternately to improve efficiency and compressing rate. In decompression circuit, an integrated State machine control module is adopted to save hardware resource. Through hardware description and language programming, the circuits finally reach function simulation and timing simulation. The width of data sample is 12bits, and the dictionary storage capacity is 1K. The simulation results show the compression and decompression circuits have complete function. Compared to software method, hardware implementation can save more storage and compressing time. It has a high practical value in the future.

scholarly journals Data Compression and Vectorization of Matrix Multiplication on HXDSP

2018 ◽  
Vol 173 ◽  
pp. 03008
Author(s):  
Liu Yufu ◽  
Lang Wenhui ◽  
Jia Guangshuai
Keyword(s):  
Data Processing ◽  
Data Compression ◽  
Hardware Implementation ◽  
Matrix Multiplication ◽  
Processing Capability ◽  
Performance Requirements ◽  
Peak Point ◽  
Processing Ability ◽  
Low Efficiency ◽  
Vector Processors

In order to solve the problem of low efficiency of hardware resources and low data processing ability of vector processors, this paper uses data compression and vectorization method to realize matrix multiplication based on the HXDSP platform with the DCT algorithm in HEVC. It can make full use of the hardware resources of DSP to achieve the optimal optimization. The experimental results show that this method can achieve 32GMACS which is the peak-point multiply-accumulate capability of HXDSP. It can achieve to 2Gpixel/s for the data processing capability, which meets the performance requirements of HEVC coding standard and provides a reference for hardware implementation of HEVC.

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