A Hardware Implementation of Real Time Lossless Data Compression and Decompression Circuits

2015 ◽  
Vol 719-720 ◽  
pp. 554-560
Author(s):  
Le Yang ◽  
Zhao Yang Guo ◽  
Shan Shan Yong ◽  
Feng Guo ◽  
Xin An Wang

This paper presents a hardware implementation of real time data compression and decompression circuits based on the LZW algorithm. LZW is a dictionary based data compression, which has the advantage of fast speed, high compression, and small resource occupation. In compression circuit, the design creatively utilizes two dictionaries alternately to improve efficiency and compressing rate. In decompression circuit, an integrated State machine control module is adopted to save hardware resource. Through hardware description and language programming, the circuits finally reach function simulation and timing simulation. The width of data sample is 12bits, and the dictionary storage capacity is 1K. The simulation results show the compression and decompression circuits have complete function. Compared to software method, hardware implementation can save more storage and compressing time. It has a high practical value in the future.

2014 ◽  
Vol 519-520 ◽  
pp. 70-73 ◽  
Author(s):  
Jing Bai ◽  
Tie Cheng Pu

Aiming at storing and transmitting the real time data of energy management system in the industrial production, an online data compression technique is proposed. Firstly, the auto regression model of a group of sequence is established. Secondly, the next sampled data can be predicted by the model. If the estimated error is in the allowable range, we save the parameters of model and the beginning data. Otherwise, we save the data and repeat the method from the next sampled data. At Last, the method is applied in electricity energy data compression of a beer production. The application result verifies the effectiveness of the proposed method.


2012 ◽  
Vol 433-440 ◽  
pp. 4173-4177
Author(s):  
Jian Hu Zhan ◽  
Wen Yi Liu

The application of the lossless data compression technology in the filed of telemetry system is discussed in this paper. Based on the ARC algorithm, a real-time lossless data compression technology is proposed. By combining the TMS320C6416 and XC3S200AN FPGA, this paper designs a real-time lossless data compression device hardware system. 2048 bytes of some telemetry noise data can be compressed in 5.64ms in this system and the compression removal rate reaches 78%. What’s more, the system has solved the problem of data capacity and speed during the process of data compression , which greatly improves the efficiency of data compression.


2007 ◽  
Vol 82 (5-14) ◽  
pp. 1301-1307 ◽  
Author(s):  
J. Vega ◽  
M. Ruiz ◽  
E. Sánchez ◽  
A. Pereira ◽  
A. Portas ◽  
...  

2011 ◽  
Vol 268-270 ◽  
pp. 110-115
Author(s):  
Ling Ma ◽  
Ke Zhu Song ◽  
Jun Feng Yang ◽  
Ping Cao

According to the architecture characteristics of the mass data acquisition system in marine seismic exploration, this paper designed a real-time data processing algorithm which can convert the collected time-sequence data to channel-sequence data. A hardware implementation of the algorithm based on FPGA+DDR SDRAM is developed to complete the whole conversion process. Here, FPGA is used to achieve time sequence data receiving, analyzing, preliminary processing and the interface to DDR SDRAM. Two DDR SDRAM’s are used in ping-pang mode to store time-sequence data and to cooperate with FPGA in realizing time-to-channel sequence data conversion. Test results showed that, after applying the algorithm to the FCI in high-precision marine seismic data acquisition and recording system, this arithmetic could realize caching collected data without redundancy and converting data from time sequence to channel sequence without dead time, besides, this algorithm also greatly improved the efficiency and reliability of data processing.


2018 ◽  
Vol 7 (2.21) ◽  
pp. 127
Author(s):  
Shrikanth Shirakol ◽  
Akshata Koparde ◽  
Sandhya . ◽  
Shravan Kulkarni ◽  
Yogesh Kini

In this paper, an optimized dual stage architecture is proposed which is the combination of Lempel-Ziv-Welch (LZW) Algorithm at the first phase and Arithmetic Coding being the later part of Architecture. LZW Algorithm is a lossless compression algorithm and code here for each character is available in the dictionary which reduces 5-bits per cycle as compared to ASCII. In arithmetic coding the numbers are represented by an interval of real numbers from zero to one according to their probabilities. It is an entropy coding and is lossless in nature. The text information is allowed to pass through the proposed architecture and it gets compressed to the higher rate.  


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